gd32f30x_fwdgt.c 7.0 KB

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  1. /*!
  2. \file gd32f30x_fwdgt.c
  3. \brief FWDGT driver
  4. \version 2017-02-10, V1.0.0, firmware for GD32F30x
  5. \version 2018-10-10, V1.1.0, firmware for GD32F30x
  6. \version 2018-12-25, V2.0.0, firmware for GD32F30x
  7. \version 2020-09-30, V2.1.0, firmware for GD32F30x
  8. */
  9. /*
  10. Copyright (c) 2020, GigaDevice Semiconductor Inc.
  11. Redistribution and use in source and binary forms, with or without modification,
  12. are permitted provided that the following conditions are met:
  13. 1. Redistributions of source code must retain the above copyright notice, this
  14. list of conditions and the following disclaimer.
  15. 2. Redistributions in binary form must reproduce the above copyright notice,
  16. this list of conditions and the following disclaimer in the documentation
  17. and/or other materials provided with the distribution.
  18. 3. Neither the name of the copyright holder nor the names of its contributors
  19. may be used to endorse or promote products derived from this software without
  20. specific prior written permission.
  21. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22. AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  23. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  25. INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26. NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  27. PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  28. WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29. ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  30. OF SUCH DAMAGE.
  31. */
  32. #include "gd32f30x_fwdgt.h"
  33. /* write value to FWDGT_CTL_CMD bit field */
  34. #define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
  35. /* write value to FWDGT_RLD_RLD bit field */
  36. #define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
  37. /*!
  38. \brief enable write access to FWDGT_PSC and FWDGT_RLD
  39. \param[in] none
  40. \param[out] none
  41. \retval none
  42. */
  43. void fwdgt_write_enable(void)
  44. {
  45. FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
  46. }
  47. /*!
  48. \brief disable write access to FWDGT_PSC and FWDGT_RLD
  49. \param[in] none
  50. \param[out] none
  51. \retval none
  52. */
  53. void fwdgt_write_disable(void)
  54. {
  55. FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
  56. }
  57. /*!
  58. \brief start the free watchdog timer counter
  59. \param[in] none
  60. \param[out] none
  61. \retval none
  62. */
  63. void fwdgt_enable(void)
  64. {
  65. FWDGT_CTL = FWDGT_KEY_ENABLE;
  66. }
  67. /*!
  68. \brief configure the free watchdog timer counter prescaler value
  69. \param[in] prescaler_value: specify prescaler value
  70. only one parameter can be selected which is shown as below:
  71. \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
  72. \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
  73. \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
  74. \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
  75. \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
  76. \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
  77. \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
  78. \param[out] none
  79. \retval ErrStatus: ERROR or SUCCESS
  80. */
  81. ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
  82. {
  83. uint32_t timeout = FWDGT_PSC_TIMEOUT;
  84. uint32_t flag_status = RESET;
  85. /* enable write access to FWDGT_PSC */
  86. FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
  87. /* wait until the PUD flag to be reset */
  88. do {
  89. flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
  90. } while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
  91. if((uint32_t)RESET != flag_status) {
  92. return ERROR;
  93. }
  94. /* configure FWDGT */
  95. FWDGT_PSC = (uint32_t)prescaler_value;
  96. return SUCCESS;
  97. }
  98. /*!
  99. \brief configure the free watchdog timer counter reload value
  100. \param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
  101. \param[out] none
  102. \retval ErrStatus: ERROR or SUCCESS
  103. */
  104. ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
  105. {
  106. uint32_t timeout = FWDGT_RLD_TIMEOUT;
  107. uint32_t flag_status = RESET;
  108. /* enable write access to FWDGT_RLD */
  109. FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
  110. /* wait until the RUD flag to be reset */
  111. do {
  112. flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
  113. } while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
  114. if((uint32_t)RESET != flag_status) {
  115. return ERROR;
  116. }
  117. FWDGT_RLD = RLD_RLD(reload_value);
  118. return SUCCESS;
  119. }
  120. /*!
  121. \brief reload the counter of FWDGT
  122. \param[in] none
  123. \param[out] none
  124. \retval none
  125. */
  126. void fwdgt_counter_reload(void)
  127. {
  128. FWDGT_CTL = FWDGT_KEY_RELOAD;
  129. }
  130. /*!
  131. \brief configure counter reload value, and prescaler divider value
  132. \param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
  133. \param[in] prescaler_div: FWDGT prescaler value
  134. only one parameter can be selected which is shown as below:
  135. \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
  136. \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
  137. \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
  138. \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
  139. \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
  140. \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
  141. \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
  142. \param[out] none
  143. \retval ErrStatus: ERROR or SUCCESS
  144. */
  145. ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
  146. {
  147. uint32_t timeout = FWDGT_PSC_TIMEOUT;
  148. uint32_t flag_status = RESET;
  149. /* enable write access to FWDGT_PSC,and FWDGT_RLD */
  150. FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
  151. /* wait until the PUD flag to be reset */
  152. do {
  153. flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
  154. } while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
  155. if((uint32_t)RESET != flag_status) {
  156. return ERROR;
  157. }
  158. /* configure FWDGT */
  159. FWDGT_PSC = (uint32_t)prescaler_div;
  160. timeout = FWDGT_RLD_TIMEOUT;
  161. /* wait until the RUD flag to be reset */
  162. do {
  163. flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
  164. } while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
  165. if((uint32_t)RESET != flag_status) {
  166. return ERROR;
  167. }
  168. FWDGT_RLD = RLD_RLD(reload_value);
  169. /* reload the counter */
  170. FWDGT_CTL = FWDGT_KEY_RELOAD;
  171. return SUCCESS;
  172. }
  173. /*!
  174. \brief get flag state of FWDGT
  175. \param[in] flag: flag to get
  176. only one parameter can be selected which is shown as below:
  177. \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
  178. \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
  179. \param[out] none
  180. \retval FlagStatus: SET or RESET
  181. */
  182. FlagStatus fwdgt_flag_get(uint16_t flag)
  183. {
  184. if(FWDGT_STAT & flag) {
  185. return SET;
  186. }
  187. return RESET;
  188. }