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- #ifndef GD32F30X_DMA_H
- #define GD32F30X_DMA_H
- #include "gd32f30x.h"
- #define DMA0 (DMA_BASE)
- #define DMA1 (DMA_BASE + 0x0400U)
- #define DMA_INTF(dmax) REG32((dmax) + 0x00U)
- #define DMA_INTC(dmax) REG32((dmax) + 0x04U)
- #define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U)
- #define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU)
- #define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U)
- #define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U)
- #define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU)
- #define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U)
- #define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U)
- #define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U)
- #define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U)
- #define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U)
- #define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U)
- #define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU)
- #define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U)
- #define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U)
- #define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU)
- #define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U)
- #define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U)
- #define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU)
- #define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U)
- #define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U)
- #define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU)
- #define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U)
- #define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U)
- #define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U)
- #define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U)
- #define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U)
- #define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U)
- #define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU)
- #define DMA_INTF_GIF BIT(0)
- #define DMA_INTF_FTFIF BIT(1)
- #define DMA_INTF_HTFIF BIT(2)
- #define DMA_INTF_ERRIF BIT(3)
- #define DMA_INTC_GIFC BIT(0)
- #define DMA_INTC_FTFIFC BIT(1)
- #define DMA_INTC_HTFIFC BIT(2)
- #define DMA_INTC_ERRIFC BIT(3)
- #define DMA_CHXCTL_CHEN BIT(0)
- #define DMA_CHXCTL_FTFIE BIT(1)
- #define DMA_CHXCTL_HTFIE BIT(2)
- #define DMA_CHXCTL_ERRIE BIT(3)
- #define DMA_CHXCTL_DIR BIT(4)
- #define DMA_CHXCTL_CMEN BIT(5)
- #define DMA_CHXCTL_PNAGA BIT(6)
- #define DMA_CHXCTL_MNAGA BIT(7)
- #define DMA_CHXCTL_PWIDTH BITS(8,9)
- #define DMA_CHXCTL_MWIDTH BITS(10,11)
- #define DMA_CHXCTL_PRIO BITS(12,13)
- #define DMA_CHXCTL_M2M BIT(14)
- #define DMA_CHXCNT_CNT BITS(0,15)
- #define DMA_CHXPADDR_PADDR BITS(0,31)
- #define DMA_CHXMADDR_MADDR BITS(0,31)
- typedef enum
- {
- DMA_CH0 = 0,
- DMA_CH1,
- DMA_CH2,
- DMA_CH3,
- DMA_CH4,
- DMA_CH5,
- DMA_CH6
- } dma_channel_enum;
- typedef struct
- {
- uint32_t periph_addr;
- uint32_t periph_width;
- uint32_t memory_addr;
- uint32_t memory_width;
- uint32_t number;
- uint32_t priority;
- uint8_t periph_inc;
- uint8_t memory_inc;
- uint8_t direction;
- } dma_parameter_struct;
- #define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U))
- #define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel))
- #define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel))
- #define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel))
- #define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel))
- #define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U)
- #define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U)
- #define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U)
- #define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U)
- #define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \
- DMA_INTF_HTFIF | DMA_INTF_ERRIF)
- #define DMA_INT_FLAG_G DMA_INTF_GIF
- #define DMA_INT_FLAG_FTF DMA_INTF_FTFIF
- #define DMA_INT_FLAG_HTF DMA_INTF_HTFIF
- #define DMA_INT_FLAG_ERR DMA_INTF_ERRIF
- #define DMA_FLAG_G DMA_INTF_GIF
- #define DMA_FLAG_FTF DMA_INTF_FTFIF
- #define DMA_FLAG_HTF DMA_INTF_HTFIF
- #define DMA_FLAG_ERR DMA_INTF_ERRIF
- #define DMA_INT_FTF DMA_CHXCTL_FTFIE
- #define DMA_INT_HTF DMA_CHXCTL_HTFIE
- #define DMA_INT_ERR DMA_CHXCTL_ERRIE
-
- #define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x0000U)
- #define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x0001U)
- #define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x0000U)
- #define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x0001U)
- #define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x0000U)
- #define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x0001U)
- #define CHCTL_PWIDTH(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
- #define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0)
- #define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1)
- #define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2)
- #define CHCTL_MWIDTH(regval) (BITS(10,11) & ((uint32_t)(regval) << 10))
- #define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0)
- #define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1)
- #define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2)
- #define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
- #define DMA_PRIORITY_LOW CHCTL_PRIO(0)
- #define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1)
- #define DMA_PRIORITY_HIGH CHCTL_PRIO(2)
- #define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3)
- #define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U)
- #define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U)
- #define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT
- void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx);
- void dma_struct_para_init(dma_parameter_struct* init_struct);
- void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct* init_struct);
- void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx);
- void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx);
- void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx);
- void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx);
- void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx);
- void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx);
- void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
- void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
- void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number);
- uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx);
- void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority);
- void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth);
- void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth);
- void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
- void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
- void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
- void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
- void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction);
- FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
- void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
- FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
- void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
- void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
- void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
- #endif
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