core_cmFunc.h 15 KB

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  1. /**************************************************************************//**
  2. * @file core_cmFunc.h
  3. * @brief CMSIS Cortex-M Core Function Access Header File
  4. * @version V3.01
  5. * @date 06. March 2012
  6. *
  7. * @note
  8. * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
  9. *
  10. * @par
  11. * ARM Limited (ARM) is supplying this software for use with Cortex-M
  12. * processor based microcontrollers. This file can be freely distributed
  13. * within development tools that are supporting such ARM based processors.
  14. *
  15. * @par
  16. * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  17. * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  18. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  19. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  20. * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  21. *
  22. ******************************************************************************/
  23. #ifndef __CORE_CMFUNC_H
  24. #define __CORE_CMFUNC_H
  25. /* ########################### Core Function Access ########################### */
  26. /** \ingroup CMSIS_Core_FunctionInterface
  27. \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
  28. @{
  29. */
  30. #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
  31. /* ARM armcc specific functions */
  32. #if (__ARMCC_VERSION < 400677)
  33. #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
  34. #endif
  35. /* intrinsic void __enable_irq(); */
  36. /* intrinsic void __disable_irq(); */
  37. /** \brief Get Control Register
  38. This function returns the content of the Control Register.
  39. \return Control Register value
  40. */
  41. __STATIC_INLINE uint32_t __get_CONTROL(void)
  42. {
  43. register uint32_t __regControl __ASM("control");
  44. return(__regControl);
  45. }
  46. /** \brief Set Control Register
  47. This function writes the given value to the Control Register.
  48. \param [in] control Control Register value to set
  49. */
  50. __STATIC_INLINE void __set_CONTROL(uint32_t control)
  51. {
  52. register uint32_t __regControl __ASM("control");
  53. __regControl = control;
  54. }
  55. /** \brief Get IPSR Register
  56. This function returns the content of the IPSR Register.
  57. \return IPSR Register value
  58. */
  59. __STATIC_INLINE uint32_t __get_IPSR(void)
  60. {
  61. register uint32_t __regIPSR __ASM("ipsr");
  62. return(__regIPSR);
  63. }
  64. /** \brief Get APSR Register
  65. This function returns the content of the APSR Register.
  66. \return APSR Register value
  67. */
  68. __STATIC_INLINE uint32_t __get_APSR(void)
  69. {
  70. register uint32_t __regAPSR __ASM("apsr");
  71. return(__regAPSR);
  72. }
  73. /** \brief Get xPSR Register
  74. This function returns the content of the xPSR Register.
  75. \return xPSR Register value
  76. */
  77. __STATIC_INLINE uint32_t __get_xPSR(void)
  78. {
  79. register uint32_t __regXPSR __ASM("xpsr");
  80. return(__regXPSR);
  81. }
  82. /** \brief Get Process Stack Pointer
  83. This function returns the current value of the Process Stack Pointer (PSP).
  84. \return PSP Register value
  85. */
  86. __STATIC_INLINE uint32_t __get_PSP(void)
  87. {
  88. register uint32_t __regProcessStackPointer __ASM("psp");
  89. return(__regProcessStackPointer);
  90. }
  91. /** \brief Set Process Stack Pointer
  92. This function assigns the given value to the Process Stack Pointer (PSP).
  93. \param [in] topOfProcStack Process Stack Pointer value to set
  94. */
  95. __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
  96. {
  97. register uint32_t __regProcessStackPointer __ASM("psp");
  98. __regProcessStackPointer = topOfProcStack;
  99. }
  100. /** \brief Get Main Stack Pointer
  101. This function returns the current value of the Main Stack Pointer (MSP).
  102. \return MSP Register value
  103. */
  104. __STATIC_INLINE uint32_t __get_MSP(void)
  105. {
  106. register uint32_t __regMainStackPointer __ASM("msp");
  107. return(__regMainStackPointer);
  108. }
  109. /** \brief Set Main Stack Pointer
  110. This function assigns the given value to the Main Stack Pointer (MSP).
  111. \param [in] topOfMainStack Main Stack Pointer value to set
  112. */
  113. __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
  114. {
  115. register uint32_t __regMainStackPointer __ASM("msp");
  116. __regMainStackPointer = topOfMainStack;
  117. }
  118. /** \brief Get Priority Mask
  119. This function returns the current state of the priority mask bit from the Priority Mask Register.
  120. \return Priority Mask value
  121. */
  122. __STATIC_INLINE uint32_t __get_PRIMASK(void)
  123. {
  124. register uint32_t __regPriMask __ASM("primask");
  125. return(__regPriMask);
  126. }
  127. /** \brief Set Priority Mask
  128. This function assigns the given value to the Priority Mask Register.
  129. \param [in] priMask Priority Mask
  130. */
  131. __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
  132. {
  133. register uint32_t __regPriMask __ASM("primask");
  134. __regPriMask = (priMask);
  135. }
  136. #if (__CORTEX_M >= 0x03)
  137. /** \brief Enable FIQ
  138. This function enables FIQ interrupts by clearing the F-bit in the CPSR.
  139. Can only be executed in Privileged modes.
  140. */
  141. #define __enable_fault_irq __enable_fiq
  142. /** \brief Disable FIQ
  143. This function disables FIQ interrupts by setting the F-bit in the CPSR.
  144. Can only be executed in Privileged modes.
  145. */
  146. #define __disable_fault_irq __disable_fiq
  147. /** \brief Get Base Priority
  148. This function returns the current value of the Base Priority register.
  149. \return Base Priority register value
  150. */
  151. __STATIC_INLINE uint32_t __get_BASEPRI(void)
  152. {
  153. register uint32_t __regBasePri __ASM("basepri");
  154. return(__regBasePri);
  155. }
  156. /** \brief Set Base Priority
  157. This function assigns the given value to the Base Priority register.
  158. \param [in] basePri Base Priority value to set
  159. */
  160. __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
  161. {
  162. register uint32_t __regBasePri __ASM("basepri");
  163. __regBasePri = (basePri & 0xff);
  164. }
  165. /** \brief Get Fault Mask
  166. This function returns the current value of the Fault Mask register.
  167. \return Fault Mask register value
  168. */
  169. __STATIC_INLINE uint32_t __get_FAULTMASK(void)
  170. {
  171. register uint32_t __regFaultMask __ASM("faultmask");
  172. return(__regFaultMask);
  173. }
  174. /** \brief Set Fault Mask
  175. This function assigns the given value to the Fault Mask register.
  176. \param [in] faultMask Fault Mask value to set
  177. */
  178. __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
  179. {
  180. register uint32_t __regFaultMask __ASM("faultmask");
  181. __regFaultMask = (faultMask & (uint32_t)1);
  182. }
  183. #endif /* (__CORTEX_M >= 0x03) */
  184. #if (__CORTEX_M == 0x04)
  185. /** \brief Get FPSCR
  186. This function returns the current value of the Floating Point Status/Control register.
  187. \return Floating Point Status/Control register value
  188. */
  189. __STATIC_INLINE uint32_t __get_FPSCR(void)
  190. {
  191. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  192. register uint32_t __regfpscr __ASM("fpscr");
  193. return(__regfpscr);
  194. #else
  195. return(0);
  196. #endif
  197. }
  198. /** \brief Set FPSCR
  199. This function assigns the given value to the Floating Point Status/Control register.
  200. \param [in] fpscr Floating Point Status/Control value to set
  201. */
  202. __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
  203. {
  204. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  205. register uint32_t __regfpscr __ASM("fpscr");
  206. __regfpscr = (fpscr);
  207. #endif
  208. }
  209. #endif /* (__CORTEX_M == 0x04) */
  210. #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
  211. /* IAR iccarm specific functions */
  212. #include <cmsis_iar.h>
  213. #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
  214. /* TI CCS specific functions */
  215. #include <cmsis_ccs.h>
  216. #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
  217. /* GNU gcc specific functions */
  218. /** \brief Enable IRQ Interrupts
  219. This function enables IRQ interrupts by clearing the I-bit in the CPSR.
  220. Can only be executed in Privileged modes.
  221. */
  222. __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
  223. {
  224. __ASM volatile ("cpsie i");
  225. }
  226. /** \brief Disable IRQ Interrupts
  227. This function disables IRQ interrupts by setting the I-bit in the CPSR.
  228. Can only be executed in Privileged modes.
  229. */
  230. __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
  231. {
  232. __ASM volatile ("cpsid i");
  233. }
  234. /** \brief Get Control Register
  235. This function returns the content of the Control Register.
  236. \return Control Register value
  237. */
  238. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
  239. {
  240. uint32_t result;
  241. __ASM volatile ("MRS %0, control" : "=r" (result) );
  242. return(result);
  243. }
  244. /** \brief Set Control Register
  245. This function writes the given value to the Control Register.
  246. \param [in] control Control Register value to set
  247. */
  248. __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
  249. {
  250. __ASM volatile ("MSR control, %0" : : "r" (control) );
  251. }
  252. /** \brief Get IPSR Register
  253. This function returns the content of the IPSR Register.
  254. \return IPSR Register value
  255. */
  256. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
  257. {
  258. uint32_t result;
  259. __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
  260. return(result);
  261. }
  262. /** \brief Get APSR Register
  263. This function returns the content of the APSR Register.
  264. \return APSR Register value
  265. */
  266. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
  267. {
  268. uint32_t result;
  269. __ASM volatile ("MRS %0, apsr" : "=r" (result) );
  270. return(result);
  271. }
  272. /** \brief Get xPSR Register
  273. This function returns the content of the xPSR Register.
  274. \return xPSR Register value
  275. */
  276. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
  277. {
  278. uint32_t result;
  279. __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
  280. return(result);
  281. }
  282. /** \brief Get Process Stack Pointer
  283. This function returns the current value of the Process Stack Pointer (PSP).
  284. \return PSP Register value
  285. */
  286. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
  287. {
  288. register uint32_t result;
  289. __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
  290. return(result);
  291. }
  292. /** \brief Set Process Stack Pointer
  293. This function assigns the given value to the Process Stack Pointer (PSP).
  294. \param [in] topOfProcStack Process Stack Pointer value to set
  295. */
  296. __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
  297. {
  298. __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
  299. }
  300. /** \brief Get Main Stack Pointer
  301. This function returns the current value of the Main Stack Pointer (MSP).
  302. \return MSP Register value
  303. */
  304. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
  305. {
  306. register uint32_t result;
  307. __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
  308. return(result);
  309. }
  310. /** \brief Set Main Stack Pointer
  311. This function assigns the given value to the Main Stack Pointer (MSP).
  312. \param [in] topOfMainStack Main Stack Pointer value to set
  313. */
  314. __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
  315. {
  316. __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
  317. }
  318. /** \brief Get Priority Mask
  319. This function returns the current state of the priority mask bit from the Priority Mask Register.
  320. \return Priority Mask value
  321. */
  322. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
  323. {
  324. uint32_t result;
  325. __ASM volatile ("MRS %0, primask" : "=r" (result) );
  326. return(result);
  327. }
  328. /** \brief Set Priority Mask
  329. This function assigns the given value to the Priority Mask Register.
  330. \param [in] priMask Priority Mask
  331. */
  332. __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
  333. {
  334. __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
  335. }
  336. #if (__CORTEX_M >= 0x03)
  337. /** \brief Enable FIQ
  338. This function enables FIQ interrupts by clearing the F-bit in the CPSR.
  339. Can only be executed in Privileged modes.
  340. */
  341. __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
  342. {
  343. __ASM volatile ("cpsie f");
  344. }
  345. /** \brief Disable FIQ
  346. This function disables FIQ interrupts by setting the F-bit in the CPSR.
  347. Can only be executed in Privileged modes.
  348. */
  349. __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
  350. {
  351. __ASM volatile ("cpsid f");
  352. }
  353. /** \brief Get Base Priority
  354. This function returns the current value of the Base Priority register.
  355. \return Base Priority register value
  356. */
  357. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
  358. {
  359. uint32_t result;
  360. __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
  361. return(result);
  362. }
  363. /** \brief Set Base Priority
  364. This function assigns the given value to the Base Priority register.
  365. \param [in] basePri Base Priority value to set
  366. */
  367. __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
  368. {
  369. __ASM volatile ("MSR basepri, %0" : : "r" (value) );
  370. }
  371. /** \brief Get Fault Mask
  372. This function returns the current value of the Fault Mask register.
  373. \return Fault Mask register value
  374. */
  375. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
  376. {
  377. uint32_t result;
  378. __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
  379. return(result);
  380. }
  381. /** \brief Set Fault Mask
  382. This function assigns the given value to the Fault Mask register.
  383. \param [in] faultMask Fault Mask value to set
  384. */
  385. __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
  386. {
  387. __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
  388. }
  389. #endif /* (__CORTEX_M >= 0x03) */
  390. #if (__CORTEX_M == 0x04)
  391. /** \brief Get FPSCR
  392. This function returns the current value of the Floating Point Status/Control register.
  393. \return Floating Point Status/Control register value
  394. */
  395. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
  396. {
  397. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  398. uint32_t result;
  399. __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
  400. return(result);
  401. #else
  402. return(0);
  403. #endif
  404. }
  405. /** \brief Set FPSCR
  406. This function assigns the given value to the Floating Point Status/Control register.
  407. \param [in] fpscr Floating Point Status/Control value to set
  408. */
  409. __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
  410. {
  411. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  412. __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
  413. #endif
  414. }
  415. #endif /* (__CORTEX_M == 0x04) */
  416. #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
  417. /* TASKING carm specific functions */
  418. /*
  419. * The CMSIS functions have been implemented as intrinsics in the compiler.
  420. * Please use "carm -?i" to get an up to date list of all instrinsics,
  421. * Including the CMSIS ones.
  422. */
  423. #endif
  424. /*@} end of CMSIS_Core_RegAccFunctions */
  425. #endif /* __CORE_CMFUNC_H */