startup_gd32f30x_xd.s 17 KB

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  1. ;/*!
  2. ; \file startup_gd32f30x_xd.s
  3. ; \brief start up file
  4. ;
  5. ; \version 2017-02-10, V1.0.0, firmware for GD32F30x
  6. ; \version 2018-10-10, V1.1.0, firmware for GD32F30x
  7. ; \version 2018-12-25, V2.0.0, firmware for GD32F30x
  8. ; \version 2020-09-30, V2.1.0, firmware for GD32F30x
  9. ;*/
  10. ;
  11. ;/*
  12. ; Copyright (c) 2020, GigaDevice Semiconductor Inc.
  13. ; Redistribution and use in source and binary forms, with or without modification,
  14. ;are permitted provided that the following conditions are met:
  15. ;
  16. ; 1. Redistributions of source code must retain the above copyright notice, this
  17. ; list of conditions and the following disclaimer.
  18. ; 2. Redistributions in binary form must reproduce the above copyright notice,
  19. ; this list of conditions and the following disclaimer in the documentation
  20. ; and/or other materials provided with the distribution.
  21. ; 3. Neither the name of the copyright holder nor the names of its contributors
  22. ; may be used to endorse or promote products derived from this software without
  23. ; specific prior written permission.
  24. ;
  25. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  26. ;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  27. ;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  28. ;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  29. ;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  30. ;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31. ;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32. ;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33. ;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  34. ;OF SUCH DAMAGE.
  35. ;*/
  36. ; <h> Stack Configuration
  37. ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
  38. ; </h>
  39. Stack_Size EQU 0x00000400
  40. AREA STACK, NOINIT, READWRITE, ALIGN=3
  41. Stack_Mem SPACE Stack_Size
  42. __initial_sp
  43. ; <h> Heap Configuration
  44. ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
  45. ; </h>
  46. Heap_Size EQU 0x00000400
  47. AREA HEAP, NOINIT, READWRITE, ALIGN=3
  48. __heap_base
  49. Heap_Mem SPACE Heap_Size
  50. __heap_limit
  51. PRESERVE8
  52. THUMB
  53. ; /* reset Vector Mapped to at Address 0 */
  54. AREA RESET, DATA, READONLY
  55. EXPORT __Vectors
  56. EXPORT __Vectors_End
  57. EXPORT __Vectors_Size
  58. __Vectors DCD __initial_sp ; Top of Stack
  59. DCD Reset_Handler ; Reset Handler
  60. DCD NMI_Handler ; NMI Handler
  61. DCD HardFault_Handler ; Hard Fault Handler
  62. DCD MemManage_Handler ; MPU Fault Handler
  63. DCD BusFault_Handler ; Bus Fault Handler
  64. DCD UsageFault_Handler ; Usage Fault Handler
  65. DCD 0 ; Reserved
  66. DCD 0 ; Reserved
  67. DCD 0 ; Reserved
  68. DCD 0 ; Reserved
  69. DCD SVC_Handler ; SVCall Handler
  70. DCD DebugMon_Handler ; Debug Monitor Handler
  71. DCD 0 ; Reserved
  72. DCD PendSV_Handler ; PendSV Handler
  73. DCD SysTick_Handler ; SysTick Handler
  74. ; /* external interrupts handler */
  75. DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
  76. DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
  77. DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
  78. DCD RTC_IRQHandler ; 19:RTC through EXTI Line
  79. DCD FMC_IRQHandler ; 20:FMC
  80. DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
  81. DCD EXTI0_IRQHandler ; 22:EXTI Line 0
  82. DCD EXTI1_IRQHandler ; 23:EXTI Line 1
  83. DCD EXTI2_IRQHandler ; 24:EXTI Line 2
  84. DCD EXTI3_IRQHandler ; 25:EXTI Line 3
  85. DCD EXTI4_IRQHandler ; 26:EXTI Line 4
  86. DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
  87. DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
  88. DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
  89. DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
  90. DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
  91. DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
  92. DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
  93. DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
  94. DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD HP and CAN0 TX
  95. DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD LP and CAN0 RX0
  96. DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
  97. DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
  98. DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
  99. DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
  100. DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
  101. DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
  102. DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
  103. DCD TIMER1_IRQHandler ; 44:TIMER1
  104. DCD TIMER2_IRQHandler ; 45:TIMER2
  105. DCD TIMER3_IRQHandler ; 46:TIMER3
  106. DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
  107. DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
  108. DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
  109. DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
  110. DCD SPI0_IRQHandler ; 51:SPI0
  111. DCD SPI1_IRQHandler ; 52:SPI1
  112. DCD USART0_IRQHandler ; 53:USART0
  113. DCD USART1_IRQHandler ; 54:USART1
  114. DCD USART2_IRQHandler ; 55:USART2
  115. DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
  116. DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
  117. DCD USBD_WKUP_IRQHandler ; 58:USBD Wakeup
  118. DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
  119. DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
  120. DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
  121. DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
  122. DCD ADC2_IRQHandler ; 63:ADC2
  123. DCD EXMC_IRQHandler ; 64:EXMC
  124. DCD SDIO_IRQHandler ; 65:SDIO
  125. DCD TIMER4_IRQHandler ; 66:TIMER4
  126. DCD SPI2_IRQHandler ; 67:SPI2
  127. DCD UART3_IRQHandler ; 68:UART3
  128. DCD UART4_IRQHandler ; 69:UART4
  129. DCD TIMER5_IRQHandler ; 70:TIMER5
  130. DCD TIMER6_IRQHandler ; 71:TIMER6
  131. DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
  132. DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
  133. DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
  134. DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4
  135. __Vectors_End
  136. __Vectors_Size EQU __Vectors_End - __Vectors
  137. AREA |.text|, CODE, READONLY
  138. ;/* reset Handler */
  139. Reset_Handler PROC
  140. EXPORT Reset_Handler [WEAK]
  141. IMPORT SystemInit
  142. IMPORT __main
  143. LDR R0, =SystemInit
  144. BLX R0
  145. LDR R0, =__main
  146. BX R0
  147. ENDP
  148. ;/* dummy Exception Handlers */
  149. NMI_Handler PROC
  150. EXPORT NMI_Handler [WEAK]
  151. B .
  152. ENDP
  153. HardFault_Handler\
  154. PROC
  155. EXPORT HardFault_Handler [WEAK]
  156. B .
  157. ENDP
  158. MemManage_Handler\
  159. PROC
  160. EXPORT MemManage_Handler [WEAK]
  161. B .
  162. ENDP
  163. BusFault_Handler\
  164. PROC
  165. EXPORT BusFault_Handler [WEAK]
  166. B .
  167. ENDP
  168. UsageFault_Handler\
  169. PROC
  170. EXPORT UsageFault_Handler [WEAK]
  171. B .
  172. ENDP
  173. SVC_Handler PROC
  174. EXPORT SVC_Handler [WEAK]
  175. B .
  176. ENDP
  177. DebugMon_Handler\
  178. PROC
  179. EXPORT DebugMon_Handler [WEAK]
  180. B .
  181. ENDP
  182. PendSV_Handler\
  183. PROC
  184. EXPORT PendSV_Handler [WEAK]
  185. B .
  186. ENDP
  187. SysTick_Handler\
  188. PROC
  189. EXPORT SysTick_Handler [WEAK]
  190. B .
  191. ENDP
  192. Default_Handler PROC
  193. ; /* external interrupts handler */
  194. EXPORT WWDGT_IRQHandler [WEAK]
  195. EXPORT LVD_IRQHandler [WEAK]
  196. EXPORT TAMPER_IRQHandler [WEAK]
  197. EXPORT RTC_IRQHandler [WEAK]
  198. EXPORT FMC_IRQHandler [WEAK]
  199. EXPORT RCU_CTC_IRQHandler [WEAK]
  200. EXPORT EXTI0_IRQHandler [WEAK]
  201. EXPORT EXTI1_IRQHandler [WEAK]
  202. EXPORT EXTI2_IRQHandler [WEAK]
  203. EXPORT EXTI3_IRQHandler [WEAK]
  204. EXPORT EXTI4_IRQHandler [WEAK]
  205. EXPORT DMA0_Channel0_IRQHandler [WEAK]
  206. EXPORT DMA0_Channel1_IRQHandler [WEAK]
  207. EXPORT DMA0_Channel2_IRQHandler [WEAK]
  208. EXPORT DMA0_Channel3_IRQHandler [WEAK]
  209. EXPORT DMA0_Channel4_IRQHandler [WEAK]
  210. EXPORT DMA0_Channel5_IRQHandler [WEAK]
  211. EXPORT DMA0_Channel6_IRQHandler [WEAK]
  212. EXPORT ADC0_1_IRQHandler [WEAK]
  213. EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK]
  214. EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK]
  215. EXPORT CAN0_RX1_IRQHandler [WEAK]
  216. EXPORT CAN0_EWMC_IRQHandler [WEAK]
  217. EXPORT EXTI5_9_IRQHandler [WEAK]
  218. EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
  219. EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
  220. EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
  221. EXPORT TIMER0_Channel_IRQHandler [WEAK]
  222. EXPORT TIMER1_IRQHandler [WEAK]
  223. EXPORT TIMER2_IRQHandler [WEAK]
  224. EXPORT TIMER3_IRQHandler [WEAK]
  225. EXPORT I2C0_EV_IRQHandler [WEAK]
  226. EXPORT I2C0_ER_IRQHandler [WEAK]
  227. EXPORT I2C1_EV_IRQHandler [WEAK]
  228. EXPORT I2C1_ER_IRQHandler [WEAK]
  229. EXPORT SPI0_IRQHandler [WEAK]
  230. EXPORT SPI1_IRQHandler [WEAK]
  231. EXPORT USART0_IRQHandler [WEAK]
  232. EXPORT USART1_IRQHandler [WEAK]
  233. EXPORT USART2_IRQHandler [WEAK]
  234. EXPORT EXTI10_15_IRQHandler [WEAK]
  235. EXPORT RTC_Alarm_IRQHandler [WEAK]
  236. EXPORT USBD_WKUP_IRQHandler [WEAK]
  237. EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
  238. EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
  239. EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
  240. EXPORT TIMER7_Channel_IRQHandler [WEAK]
  241. EXPORT ADC2_IRQHandler [WEAK]
  242. EXPORT EXMC_IRQHandler [WEAK]
  243. EXPORT SDIO_IRQHandler [WEAK]
  244. EXPORT TIMER4_IRQHandler [WEAK]
  245. EXPORT SPI2_IRQHandler [WEAK]
  246. EXPORT UART3_IRQHandler [WEAK]
  247. EXPORT UART4_IRQHandler [WEAK]
  248. EXPORT TIMER5_IRQHandler [WEAK]
  249. EXPORT TIMER6_IRQHandler [WEAK]
  250. EXPORT DMA1_Channel0_IRQHandler [WEAK]
  251. EXPORT DMA1_Channel1_IRQHandler [WEAK]
  252. EXPORT DMA1_Channel2_IRQHandler [WEAK]
  253. EXPORT DMA1_Channel3_4_IRQHandler [WEAK]
  254. ;/* external interrupts handler */
  255. WWDGT_IRQHandler
  256. LVD_IRQHandler
  257. TAMPER_IRQHandler
  258. RTC_IRQHandler
  259. FMC_IRQHandler
  260. RCU_CTC_IRQHandler
  261. EXTI0_IRQHandler
  262. EXTI1_IRQHandler
  263. EXTI2_IRQHandler
  264. EXTI3_IRQHandler
  265. EXTI4_IRQHandler
  266. DMA0_Channel0_IRQHandler
  267. DMA0_Channel1_IRQHandler
  268. DMA0_Channel2_IRQHandler
  269. DMA0_Channel3_IRQHandler
  270. DMA0_Channel4_IRQHandler
  271. DMA0_Channel5_IRQHandler
  272. DMA0_Channel6_IRQHandler
  273. ADC0_1_IRQHandler
  274. USBD_HP_CAN0_TX_IRQHandler
  275. USBD_LP_CAN0_RX0_IRQHandler
  276. CAN0_RX1_IRQHandler
  277. CAN0_EWMC_IRQHandler
  278. EXTI5_9_IRQHandler
  279. TIMER0_BRK_TIMER8_IRQHandler
  280. TIMER0_UP_TIMER9_IRQHandler
  281. TIMER0_TRG_CMT_TIMER10_IRQHandler
  282. TIMER0_Channel_IRQHandler
  283. TIMER1_IRQHandler
  284. TIMER2_IRQHandler
  285. TIMER3_IRQHandler
  286. I2C0_EV_IRQHandler
  287. I2C0_ER_IRQHandler
  288. I2C1_EV_IRQHandler
  289. I2C1_ER_IRQHandler
  290. SPI0_IRQHandler
  291. SPI1_IRQHandler
  292. USART0_IRQHandler
  293. USART1_IRQHandler
  294. USART2_IRQHandler
  295. EXTI10_15_IRQHandler
  296. RTC_Alarm_IRQHandler
  297. USBD_WKUP_IRQHandler
  298. TIMER7_BRK_TIMER11_IRQHandler
  299. TIMER7_UP_TIMER12_IRQHandler
  300. TIMER7_TRG_CMT_TIMER13_IRQHandler
  301. TIMER7_Channel_IRQHandler
  302. ADC2_IRQHandler
  303. EXMC_IRQHandler
  304. SDIO_IRQHandler
  305. TIMER4_IRQHandler
  306. SPI2_IRQHandler
  307. UART3_IRQHandler
  308. UART4_IRQHandler
  309. TIMER5_IRQHandler
  310. TIMER6_IRQHandler
  311. DMA1_Channel0_IRQHandler
  312. DMA1_Channel1_IRQHandler
  313. DMA1_Channel2_IRQHandler
  314. DMA1_Channel3_4_IRQHandler
  315. B .
  316. ENDP
  317. ALIGN
  318. ; user Initial Stack & Heap
  319. IF :DEF:__MICROLIB
  320. EXPORT __initial_sp
  321. EXPORT __heap_base
  322. EXPORT __heap_limit
  323. ELSE
  324. IMPORT __use_two_region_memory
  325. EXPORT __user_initial_stackheap
  326. __user_initial_stackheap PROC
  327. LDR R0, = Heap_Mem
  328. LDR R1, =(Stack_Mem + Stack_Size)
  329. LDR R2, = (Heap_Mem + Heap_Size)
  330. LDR R3, = Stack_Mem
  331. BX LR
  332. ENDP
  333. ALIGN
  334. ENDIF
  335. END