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|
- #include "gd32f30x_enet.h"
- #include <stdlib.h>
- #ifdef GD32F30X_CL
- #if defined (__CC_ARM)
- __align(4)
- enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM];
- __align(4)
- enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM];
- __align(4)
- uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE];
- __align(4)
- uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE];
- #elif defined ( __ICCARM__ )
- #pragma data_alignment=4
- enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM];
- #pragma data_alignment=4
- enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM];
- #pragma data_alignment=4
- uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE];
- #pragma data_alignment=4
- uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE];
- #elif defined (__GNUC__)
- enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__ ((aligned (4)));
- enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__ ((aligned (4)));
- uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__ ((aligned (4)));
- uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__ ((aligned (4)));
- #endif
- enet_descriptors_struct *dma_current_txdesc;
- enet_descriptors_struct *dma_current_rxdesc;
- enet_descriptors_struct *dma_current_ptp_txdesc = NULL;
- enet_descriptors_struct *dma_current_ptp_rxdesc = NULL;
- static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
- static uint32_t enet_unknow_err = 0U;
- static const uint16_t enet_reg_tab[] = {
- 0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0028, 0x002C, 0x0034,
- 0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, 0x1080,
-
- 0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4,
-
- 0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C,
-
- 0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048,
- 0x104C, 0x1050, 0x1054};
- static void enet_default_init(void);
- #ifndef USE_DELAY
- static void enet_delay(uint32_t ncount);
- #endif
- void enet_deinit(void)
- {
- rcu_periph_reset_enable(RCU_ENETRST);
- rcu_periph_reset_disable(RCU_ENETRST);
- enet_initpara_reset();
- }
- void enet_initpara_config(enet_option_enum option, uint32_t para)
- {
- switch(option){
- case FORWARD_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION;
- enet_initpara.forward_frame = para;
- break;
- case DMABUS_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION;
- enet_initpara.dmabus_mode = para;
- break;
- case DMA_MAXBURST_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION;
- enet_initpara.dma_maxburst = para;
- break;
- case DMA_ARBITRATION_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION;
- enet_initpara.dma_arbitration = para;
- break;
- case STORE_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)STORE_OPTION;
- enet_initpara.store_forward_mode = para;
- break;
- case DMA_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)DMA_OPTION;
- #ifndef SELECT_DESCRIPTORS_ENHANCED_MODE
- para &= ~ENET_ENHANCED_DESCRIPTOR;
- #endif
- enet_initpara.dma_function = para;
- break;
- case VLAN_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)VLAN_OPTION;
- enet_initpara.vlan_config = para;
- break;
- case FLOWCTL_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION;
- enet_initpara.flow_control = para;
- break;
- case HASHH_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)HASHH_OPTION;
- enet_initpara.hashtable_high = para;
- break;
- case HASHL_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)HASHL_OPTION;
- enet_initpara.hashtable_low = para;
- break;
- case FILTER_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)FILTER_OPTION;
- enet_initpara.framesfilter_mode = para;
- break;
- case HALFDUPLEX_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION;
- enet_initpara.halfduplex_param = para;
- break;
- case TIMER_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)TIMER_OPTION;
- enet_initpara.timer_config = para;
- break;
- case INTERFRAMEGAP_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION;
- enet_initpara.interframegap = para;
- break;
- default:
- break;
- }
- }
- ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept)
- {
- uint32_t reg_value=0U, reg_temp = 0U, temp = 0U;
- uint32_t media_temp = 0U;
- uint32_t timeout = 0U;
- uint16_t phy_value = 0U;
- ErrStatus phy_state= ERROR, enet_state = ERROR;
-
- if(ERROR == enet_phy_config()){
- _ENET_DELAY_(PHY_RESETDELAY);
- if(ERROR == enet_phy_config()){
- return enet_state;
- }
- }
-
- enet_default_init();
-
- media_temp = (uint32_t)mediamode;
-
- if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp){
-
- do{
- enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value);
- phy_value &= PHY_LINKED_STATUS;
- timeout++;
- }while((RESET == phy_value) && (timeout < PHY_READ_TO));
-
- if(PHY_READ_TO == timeout){
- return enet_state;
- }
-
- timeout = 0U;
-
- phy_value = PHY_AUTONEGOTIATION;
- phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value);
- if(!phy_state){
-
- return enet_state;
- }
-
- do{
- enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value);
- phy_value &= PHY_AUTONEGO_COMPLETE;
- timeout++;
- }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO));
-
- if(PHY_READ_TO == timeout){
- return enet_state;
- }
-
- timeout = 0U;
-
- enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value);
-
- if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){
- media_temp = ENET_MODE_FULLDUPLEX;
- }else{
- media_temp = ENET_MODE_HALFDUPLEX;
- }
-
- if((uint16_t)RESET !=(phy_value & PHY_SPEED_STATUS)){
- media_temp |= ENET_SPEEDMODE_10M;
- }else{
- media_temp |= ENET_SPEEDMODE_100M;
- }
- }else{
- phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3);
- phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1);
- phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value);
- if(!phy_state){
-
- return enet_state;
- }
-
- _ENET_DELAY_(PHY_CONFIGDELAY);
- }
-
- reg_value = ENET_MAC_CFG;
-
- reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM));
- reg_value |= media_temp;
- ENET_MAC_CFG = reg_value;
-
- if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){
- ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE;
- reg_value = ENET_DMA_CTL;
-
- reg_value &= ~ENET_DMA_CTL_DTCERFD;
- reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD);
- ENET_DMA_CTL = reg_value;
- }
-
- ENET_MAC_FRMF |= (uint32_t)recept;
-
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){
- reg_temp = enet_initpara.forward_frame;
- reg_value = ENET_MAC_CFG;
- temp = reg_temp;
-
- reg_value &= (~(ENET_MAC_CFG_TFCD |ENET_MAC_CFG_APCD));
- temp &= (ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD);
- reg_value |= temp;
- ENET_MAC_CFG = reg_value;
- reg_value = ENET_DMA_CTL;
- temp = reg_temp;
-
- reg_value &= (~(ENET_DMA_CTL_FERF |ENET_DMA_CTL_FUF));
- temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)<<2);
- reg_value |= (temp >> 2);
- ENET_DMA_CTL = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){
- temp = enet_initpara.dmabus_mode;
- reg_value = ENET_DMA_BCTL;
-
- reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \
- |ENET_DMA_BCTL_FPBL | ENET_DMA_BCTL_MB);
- reg_value |= temp;
- ENET_DMA_BCTL = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){
- temp = enet_initpara.dma_maxburst;
- reg_value = ENET_DMA_BCTL;
-
- reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP);
- reg_value |= temp;
- ENET_DMA_BCTL = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){
- temp = enet_initpara.dma_arbitration;
- reg_value = ENET_DMA_BCTL;
-
- reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB);
- reg_value |= temp;
- ENET_DMA_BCTL = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){
- temp = enet_initpara.store_forward_mode;
-
- reg_value = ENET_DMA_CTL;
-
- reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC);
- reg_value |= temp;
- ENET_DMA_CTL = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){
- reg_temp = enet_initpara.dma_function;
- reg_value = ENET_DMA_CTL;
- temp = reg_temp;
-
- reg_value &= (~(ENET_DMA_CTL_DAFRF |ENET_DMA_CTL_OSF));
- temp &= (ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF);
- reg_value |= temp;
- ENET_DMA_CTL = reg_value;
- reg_value = ENET_DMA_BCTL;
- temp = reg_temp;
-
- reg_value &= (~ENET_DMA_BCTL_DFM);
- temp &= ENET_DMA_BCTL_DFM;
- reg_value |= temp;
- ENET_DMA_BCTL = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){
- reg_temp = enet_initpara.vlan_config;
-
- reg_value = ENET_MAC_VLT;
-
- reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC);
- reg_value |= reg_temp;
- ENET_MAC_VLT = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){
- reg_temp = enet_initpara.flow_control;
-
- reg_value = ENET_MAC_FCTL;
- temp = reg_temp;
-
- reg_value &= ~(ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \
- | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN);
- temp &= (ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \
- | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN);
- reg_value |= temp;
- ENET_MAC_FCTL = reg_value;
-
- reg_value = ENET_MAC_FCTH;
- temp = reg_temp;
-
- reg_value &= ~(ENET_MAC_FCTH_RFA |ENET_MAC_FCTH_RFD);
- temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8);
- reg_value |= (temp >> 8);
- ENET_MAC_FCTH = reg_value;
- }
-
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){
- ENET_MAC_HLH = enet_initpara.hashtable_high;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){
- ENET_MAC_HLL = enet_initpara.hashtable_low;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){
- reg_temp = enet_initpara.framesfilter_mode;
-
- reg_value = ENET_MAC_FRMF;
-
- reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \
- | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \
- | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM);
- reg_value |= reg_temp;
- ENET_MAC_FRMF = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){
- reg_temp = enet_initpara.halfduplex_param;
- reg_value = ENET_MAC_CFG;
-
- reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \
- | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC);
- reg_value |= reg_temp;
- ENET_MAC_CFG = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){
- reg_temp = enet_initpara.timer_config;
-
- reg_value = ENET_MAC_CFG;
-
- reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD);
- reg_value |= reg_temp;
- ENET_MAC_CFG = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){
- reg_temp = enet_initpara.interframegap;
-
- reg_value = ENET_MAC_CFG;
-
- reg_value &= ~ENET_MAC_CFG_IGBS;
- reg_value |= reg_temp;
- ENET_MAC_CFG = reg_value;
- }
- enet_state = SUCCESS;
- return enet_state;
- }
- ErrStatus enet_software_reset(void)
- {
- uint32_t timeout = 0U;
- ErrStatus enet_state = ERROR;
- uint32_t dma_flag;
-
- ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR;
-
- do{
- dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR);
- timeout++;
- }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout));
-
- if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){
- enet_state = SUCCESS;
- }
- return enet_state;
- }
- uint32_t enet_rxframe_size_get(void)
- {
- uint32_t size = 0U;
- uint32_t status;
-
-
- status = dma_current_rxdesc->status;
-
-
- if((uint32_t)RESET != (status & ENET_RDES0_DAV)){
- return 0U;
- }
-
-
- if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) ||
- (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) ||
- (((uint32_t)RESET) == (status & ENET_RDES0_FDES))){
-
- enet_rxframe_drop();
- return 1U;
- }
- #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE
-
- if(((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FRMT) &&
- ((uint32_t)RESET) != (dma_current_rxdesc->extended_status & ENET_RDES4_IPPLDERR)){
-
- enet_rxframe_drop();
- return 1U;
- }
- #else
-
- if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) &&
- (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){
-
- enet_rxframe_drop();
- return 1U;
- }
- #endif
-
- if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) &&
- (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) &&
- (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) &&
- (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){
-
- size = GET_RDES0_FRML(status);
-
- size = size - 4U;
-
- if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (status & ENET_RDES0_FRMT))){
- size = size + 4U;
- }
- }else{
- enet_unknow_err++;
- enet_rxframe_drop();
- return 1U;
- }
-
- return size;
- }
- void enet_descriptors_chain_init(enet_dmadirection_enum direction)
- {
- uint32_t num = 0U, count = 0U, maxsize = 0U;
- uint32_t desc_status = 0U, desc_bufsize = 0U;
- enet_descriptors_struct *desc, *desc_tab;
- uint8_t *buf;
-
- if (ENET_DMA_TX == direction){
-
- desc_tab = txdesc_tab;
- buf = &tx_buff[0][0];
- count = ENET_TXBUF_NUM;
- maxsize = ENET_TXBUF_SIZE;
-
- desc_status = ENET_TDES0_TCHM;
-
- ENET_DMA_TDTADDR = (uint32_t)desc_tab;
- dma_current_txdesc = desc_tab;
- }else{
-
-
- desc_tab = rxdesc_tab;
- buf = &rx_buff[0][0];
- count = ENET_RXBUF_NUM;
- maxsize = ENET_RXBUF_SIZE;
-
- desc_status = ENET_RDES0_DAV;
-
- desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE;
-
-
- ENET_DMA_RDTADDR = (uint32_t)desc_tab;
- dma_current_rxdesc = desc_tab;
- }
- dma_current_ptp_rxdesc = NULL;
- dma_current_ptp_txdesc = NULL;
-
- for(num=0U; num < count; num++){
-
- desc = desc_tab + num;
-
- desc->status = desc_status;
- desc->control_buffer_size = desc_bufsize;
- desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
-
- if(num < (count - 1U)){
-
- desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U);
- }else{
-
-
- desc->buffer2_next_desc_addr = (uint32_t) desc_tab;
- }
- }
- }
- void enet_descriptors_ring_init(enet_dmadirection_enum direction)
- {
- uint32_t num = 0U, count = 0U, maxsize = 0U;
- uint32_t desc_status = 0U, desc_bufsize = 0U;
- enet_descriptors_struct *desc;
- enet_descriptors_struct *desc_tab;
- uint8_t *buf;
-
- ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL;
- ENET_DMA_BCTL |= DMA_BCTL_DPSL(0);
-
- if (ENET_DMA_TX == direction){
-
- desc_tab = txdesc_tab;
- buf = &tx_buff[0][0];
- count = ENET_TXBUF_NUM;
- maxsize = ENET_TXBUF_SIZE;
-
- ENET_DMA_TDTADDR = (uint32_t)desc_tab;
- dma_current_txdesc = desc_tab;
- }else{
-
-
- desc_tab = rxdesc_tab;
- buf = &rx_buff[0][0];
- count = ENET_RXBUF_NUM;
- maxsize = ENET_RXBUF_SIZE;
-
- desc_status = ENET_RDES0_DAV;
-
- desc_bufsize = ENET_RXBUF_SIZE;
-
- ENET_DMA_RDTADDR = (uint32_t)desc_tab;
- dma_current_rxdesc = desc_tab;
- }
- dma_current_ptp_rxdesc = NULL;
- dma_current_ptp_txdesc = NULL;
-
- for(num=0U; num < count; num++){
-
- desc = desc_tab + num;
-
- desc->status = desc_status;
- desc->control_buffer_size = desc_bufsize;
- desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
-
-
- if(num == (count - 1U)){
- if (ENET_DMA_TX == direction){
-
- desc->status |= ENET_TDES0_TERM;
- }else{
-
- desc->control_buffer_size |= ENET_RDES1_RERM;
- }
- }
- }
- }
- ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize)
- {
- uint32_t offset = 0U, size = 0U;
-
- if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){
- return ERROR;
- }
-
- if(NULL != buffer){
-
- if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) &&
- (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) &&
- (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){
-
- size = GET_RDES0_FRML(dma_current_rxdesc->status);
- size = size - 4U;
-
- if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){
- size = size + 4U;
- }
-
- if(size > bufsize){
- return ERROR;
- }
-
- for(offset = 0U; offset<size; offset++){
- (*(buffer + offset)) = (*(__IO uint8_t *) (uint32_t)((dma_current_rxdesc->buffer1_addr) + offset));
- }
-
- }else{
-
- return ERROR;
- }
- }
-
- dma_current_rxdesc->status = ENET_RDES0_DAV;
-
-
- if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){
-
- ENET_DMA_STAT = ENET_DMA_STAT_RBU;
-
- ENET_DMA_RPEN = 0U;
- }
-
-
-
- if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
- dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr);
- }else{
-
- if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
-
- dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
- }else{
-
- dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)));
- }
- }
- return SUCCESS;
- }
- ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length)
- {
- uint32_t offset = 0U;
- uint32_t dma_tbu_flag, dma_tu_flag;
-
- if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){
- return ERROR;
- }
-
- if(length > ENET_MAX_FRAME_SIZE){
- return ERROR;
- }
-
- if(NULL != buffer){
-
- for(offset = 0U; offset < length; offset++){
- (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset));
- }
- }
-
- dma_current_txdesc->control_buffer_size = length;
-
- dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG;
-
- dma_current_txdesc->status |= ENET_TDES0_DAV;
-
- dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU);
- dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU);
- if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){
-
- ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag);
-
- ENET_DMA_TPEN = 0U;
- }
-
-
- if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){
- dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr);
- }else{
-
- if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){
-
- dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR);
- }else{
-
- dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)));
- }
- }
- return SUCCESS;
- }
- ErrStatus enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum)
- {
- if(NULL != desc){
- desc->status &= ~ENET_TDES0_CM;
- desc->status |= checksum;
- return SUCCESS;
- }else{
- return ERROR;
- }
- }
- void enet_enable(void)
- {
- enet_tx_enable();
- enet_rx_enable();
- }
- void enet_disable(void)
- {
- enet_tx_disable();
- enet_rx_disable();
- }
-
- void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[])
- {
- REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr);
- REG32(ENET_ADDRL_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRL(paddr);
- }
-
- ErrStatus enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[], uint8_t bufsize)
- {
- if(bufsize < 6U){
- return ERROR;
- }
- paddr[0] = ENET_GET_MACADDR(mac_addr, 0U);
- paddr[1] = ENET_GET_MACADDR(mac_addr, 1U);
- paddr[2] = ENET_GET_MACADDR(mac_addr, 2U);
- paddr[3] = ENET_GET_MACADDR(mac_addr, 3U);
- paddr[4] = ENET_GET_MACADDR(mac_addr, 4U);
- paddr[5] = ENET_GET_MACADDR(mac_addr, 5U);
- return SUCCESS;
- }
- FlagStatus enet_flag_get(enet_flag_enum enet_flag)
- {
- if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))){
- return SET;
- }else{
- return RESET;
- }
- }
- void enet_flag_clear(enet_flag_clear_enum enet_flag)
- {
-
- ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag));
- }
- void enet_interrupt_enable(enet_int_enum enet_int)
- {
- if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){
-
- ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int));
- }else{
-
- ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int));
- }
- }
- void enet_interrupt_disable(enet_int_enum enet_int)
- {
- if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){
-
- ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int));
- }else{
-
- ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int));
- }
- }
- FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag)
- {
- if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))){
- return SET;
- }else{
- return RESET;
- }
- }
- void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear)
- {
-
- ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear));
- }
- void enet_tx_enable(void)
- {
- ENET_MAC_CFG |= ENET_MAC_CFG_TEN;
- enet_txfifo_flush();
- ENET_DMA_CTL |= ENET_DMA_CTL_STE;
- }
- void enet_tx_disable(void)
- {
- ENET_DMA_CTL &= ~ENET_DMA_CTL_STE;
- enet_txfifo_flush();
- ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN;
- }
- void enet_rx_enable(void)
- {
- ENET_MAC_CFG |= ENET_MAC_CFG_REN;
- ENET_DMA_CTL |= ENET_DMA_CTL_SRE;
- }
- void enet_rx_disable(void)
- {
- ENET_DMA_CTL &= ~ENET_DMA_CTL_SRE;
- ENET_MAC_CFG &= ~ENET_MAC_CFG_REN;
- }
- void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num)
- {
- uint32_t offset = 0U, max = 0U, limit = 0U;
- offset = (uint32_t)type;
- max = (uint32_t)type + num;
- limit = sizeof(enet_reg_tab)/sizeof(uint16_t);
-
- if(max > limit){
- max = limit;
- }
- for(; offset < max; offset++){
-
- *preg = REG32((ENET) + enet_reg_tab[offset]);
- preg++;
- }
- }
- uint32_t enet_debug_status_get(uint32_t mac_debug)
- {
- uint32_t temp_state = 0U;
- switch(mac_debug){
- case ENET_RX_ASYNCHRONOUS_FIFO_STATE:
- temp_state = GET_MAC_DBG_RXAFS(ENET_MAC_DBG);
- break;
- case ENET_RXFIFO_READ_STATUS:
- temp_state = GET_MAC_DBG_RXFRS(ENET_MAC_DBG);
- break;
- case ENET_RXFIFO_STATE:
- temp_state = GET_MAC_DBG_RXFS(ENET_MAC_DBG);
- break;
- case ENET_MAC_TRANSMITTER_STATUS:
- temp_state = GET_MAC_DBG_SOMT(ENET_MAC_DBG);
- break;
- case ENET_TXFIFO_READ_STATUS:
- temp_state = GET_MAC_DBG_TXFRS(ENET_MAC_DBG);
- break;
- default:
- if(RESET != (ENET_MAC_DBG & mac_debug)){
- temp_state = 0x1U;
- }
- break;
- }
- return temp_state;
- }
- void enet_address_filter_enable(enet_macaddress_enum mac_addr)
- {
- REG32(ENET_ADDRH_BASE + mac_addr) |= ENET_MAC_ADDR1H_AFE;
- }
- void enet_address_filter_disable(enet_macaddress_enum mac_addr)
- {
- REG32(ENET_ADDRH_BASE + mac_addr) &= ~ENET_MAC_ADDR1H_AFE;
- }
- void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type)
- {
- uint32_t reg;
-
- reg = REG32(ENET_ADDRH_BASE + mac_addr);
-
- reg &= ~(ENET_MAC_ADDR1H_MB | ENET_MAC_ADDR1H_SAF);
- reg |= (addr_mask | filter_type);
- REG32(ENET_ADDRH_BASE + mac_addr) = reg;
- }
-
- ErrStatus enet_phy_config(void)
- {
- uint32_t ahbclk;
- uint32_t reg;
- uint16_t phy_value;
- ErrStatus enet_state = ERROR;
-
- reg = ENET_MAC_PHY_CTL;
- reg &= ~ENET_MAC_PHY_CTL_CLR;
-
- ahbclk = rcu_clock_freq_get(CK_AHB);
-
- if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){
- reg |= ENET_MDC_HCLK_DIV16;
- }else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)){
- reg |= ENET_MDC_HCLK_DIV26;
- }else if(ENET_RANGE(ahbclk, 60000000U, 100000000U)){
- reg |= ENET_MDC_HCLK_DIV42;
- }else if((ENET_RANGE(ahbclk, 100000000U, 168000000U))||(168000000U == ahbclk)){
- reg |= ENET_MDC_HCLK_DIV62;
- }else{
- return enet_state;
- }
- ENET_MAC_PHY_CTL = reg;
-
- phy_value = PHY_RESET;
- if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){
- return enet_state;
- }
-
- _ENET_DELAY_(ENET_DELAY_TO);
-
-
- if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){
- return enet_state;
- }
-
- if(RESET == (phy_value & PHY_RESET)){
- enet_state = SUCCESS;
- }
- return enet_state;
- }
- ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue)
- {
- uint32_t reg, phy_flag;
- uint32_t timeout = 0U;
- ErrStatus enet_state = ERROR;
-
- reg = ENET_MAC_PHY_CTL;
- reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA);
- reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB);
-
- if(ENET_PHY_WRITE == direction){
- ENET_MAC_PHY_DATA = *pvalue;
- }
-
- ENET_MAC_PHY_CTL = reg;
- do{
- phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB);
- timeout++;
- }
- while((RESET != phy_flag) && (ENET_DELAY_TO != timeout));
-
- if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){
- enet_state = SUCCESS;
- }
-
- if(ENET_PHY_READ == direction){
- *pvalue = (uint16_t)ENET_MAC_PHY_DATA;
- }
- return enet_state;
- }
- ErrStatus enet_phyloopback_enable(void)
- {
- uint16_t temp_phy = 0U;
- ErrStatus phy_state = ERROR;
-
- enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
-
- temp_phy |= PHY_LOOPBACK;
-
- phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
- return phy_state;
- }
- ErrStatus enet_phyloopback_disable(void)
- {
- uint16_t temp_phy = 0U;
- ErrStatus phy_state = ERROR;
-
- enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
-
- temp_phy &= (uint16_t)~PHY_LOOPBACK;
-
- phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
- return phy_state;
- }
- void enet_forward_feature_enable(uint32_t feature)
- {
- uint32_t mask;
- mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES)));
- ENET_MAC_CFG |= mask;
- mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP)));
- ENET_DMA_CTL |= (mask >> 2);
- }
- void enet_forward_feature_disable(uint32_t feature)
- {
- uint32_t mask;
- mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES)));
- ENET_MAC_CFG &= ~mask;
- mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP)));
- ENET_DMA_CTL &= ~(mask >> 2);
- }
-
- void enet_fliter_feature_enable(uint32_t feature)
- {
- ENET_MAC_FRMF |= feature;
- }
- void enet_fliter_feature_disable(uint32_t feature)
- {
- ENET_MAC_FRMF &= ~feature;
- }
- ErrStatus enet_pauseframe_generate(void)
- {
- ErrStatus enet_state =ERROR;
- uint32_t temp = 0U;
-
- temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA;
- if(RESET == temp){
- ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA;
- enet_state = SUCCESS;
- }
- return enet_state;
- }
- void enet_pauseframe_detect_config(uint32_t detect)
- {
- ENET_MAC_FCTL &= ~ENET_MAC_FCTL_UPFDT;
- ENET_MAC_FCTL |= detect;
- }
- void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold)
- {
- ENET_MAC_FCTL &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_PLTS);
- ENET_MAC_FCTL |= (MAC_FCTL_PTM(pausetime) | pause_threshold);
- }
- void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active)
- {
- ENET_MAC_FCTH = ((deactive | active) >> 8);
- }
- void enet_flowcontrol_feature_enable(uint32_t feature)
- {
- if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){
- ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE;
- }
- feature &= ~ENET_ZERO_QUANTA_PAUSE;
- ENET_MAC_FCTL |= feature;
- }
- void enet_flowcontrol_feature_disable(uint32_t feature)
- {
- if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){
- ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE;
- }
- feature &= ~ENET_ZERO_QUANTA_PAUSE;
- ENET_MAC_FCTL &= ~feature;
- }
- uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction)
- {
- uint32_t reval;
- reval = (uint32_t)(ENET_DMA_STAT & (uint32_t)direction);
- return reval;
- }
- void enet_dmaprocess_resume(enet_dmadirection_enum direction)
- {
- if(ENET_DMA_TX == direction){
- ENET_DMA_TPEN = 0U;
- }else{
- ENET_DMA_RPEN = 0U;
- }
- }
- void enet_rxprocess_check_recovery(void)
- {
- uint32_t status;
-
- status = dma_current_rxdesc->status;
- status &= ENET_RDES0_DAV;
-
- if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) &&
- (ENET_RDES0_DAV == status)){
- dma_current_rxdesc = (enet_descriptors_struct*)ENET_DMA_CRDADDR;
- }
- }
- ErrStatus enet_txfifo_flush(void)
- {
- uint32_t flush_state;
- uint32_t timeout = 0U;
- ErrStatus enet_state = ERROR;
-
- ENET_DMA_CTL |= ENET_DMA_CTL_FTF;
-
- do{
- flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF;
- timeout++;
- }while((RESET != flush_state) && (timeout < ENET_DELAY_TO));
-
- if(RESET == flush_state){
- enet_state = SUCCESS;
- }
- return enet_state;
- }
- uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get)
- {
- uint32_t reval = 0U;
- reval = REG32((ENET) +(uint32_t)addr_get);
- return reval;
- }
- uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get)
- {
- uint32_t reval = 0xFFFFFFFFU;
- switch(info_get){
- case RXDESC_BUFFER_1_SIZE:
- reval = GET_RDES1_RB1S(desc->control_buffer_size);
- break;
- case RXDESC_BUFFER_2_SIZE:
- reval = GET_RDES1_RB2S(desc->control_buffer_size);
- break;
- case RXDESC_FRAME_LENGTH:
- reval = GET_RDES0_FRML(desc->status);
- if(reval > 4U){
- reval = reval - 4U;
-
- if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (desc->status & ENET_RDES0_FRMT))){
- reval = reval + 4U;
- }
- }else{
- reval = 0U;
- }
- break;
- case RXDESC_BUFFER_1_ADDR:
- reval = desc->buffer1_addr;
- break;
- case TXDESC_BUFFER_1_ADDR:
- reval = desc->buffer1_addr;
- break;
- case TXDESC_COLLISION_COUNT:
- reval = GET_TDES0_COCNT(desc->status);
- break;
- default:
- break;
- }
- return reval;
- }
- void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop)
- {
- uint32_t temp_counter = 0U;
- temp_counter = ENET_DMA_MFBOCNT;
- *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter);
- *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter);
- }
- FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag)
- {
- FlagStatus enet_flag = RESET;
-
- if((uint32_t)RESET != (desc->status & desc_flag)){
- enet_flag = SET;
- }
- return enet_flag;
- }
- void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag)
- {
- desc->status |= desc_flag;
- }
- void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag)
- {
- desc->status &= ~desc_flag;
- }
- void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc)
- {
- desc->control_buffer_size &= ~ENET_RDES1_DINTC;
- }
- void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time)
- {
- desc->control_buffer_size |= ENET_RDES1_DINTC;
- ENET_DMA_RSWDC = DMA_RSWDC_WDCFRS(delay_time);
- }
- void enet_rxframe_drop(void)
- {
-
- dma_current_rxdesc->status = ENET_RDES0_DAV;
-
- if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
- if(NULL != dma_current_ptp_rxdesc){
- dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr);
-
- if(0U != dma_current_ptp_rxdesc->status){
-
- dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
- }else{
-
- dma_current_ptp_rxdesc++;
- }
- }else{
- dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr);
- }
- }else{
-
- if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
-
- dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
- if(NULL != dma_current_ptp_rxdesc){
- dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
- }
- }else{
-
- dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
- if(NULL != dma_current_ptp_rxdesc){
- dma_current_ptp_rxdesc++;
- }
- }
- }
- }
- void enet_dma_feature_enable(uint32_t feature)
- {
- ENET_DMA_CTL |= feature;
- }
- void enet_dma_feature_disable(uint32_t feature)
- {
- ENET_DMA_CTL &= ~feature;
- }
- #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE
- uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status)
- {
- uint32_t reval = 0xFFFFFFFFU;
-
- switch (desc_status){
- case ENET_RDES4_IPPLDT:
- reval = GET_RDES4_IPPLDT(desc->extended_status);
- break;
- case ENET_RDES4_PTPMT:
- reval = GET_RDES4_PTPMT(desc->extended_status);
- break;
- default:
- if ((uint32_t)RESET != (desc->extended_status & desc_status)){
- reval = 1U;
- }else{
- reval = 0U;
- }
- }
-
- return reval;
- }
- void enet_desc_select_enhanced_mode(void)
- {
- ENET_DMA_BCTL |= ENET_DMA_BCTL_DFM;
- }
- void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction)
- {
- uint32_t num = 0U, count = 0U, maxsize = 0U;
- uint32_t desc_status = 0U, desc_bufsize = 0U;
- enet_descriptors_struct *desc, *desc_tab;
- uint8_t *buf;
-
-
- if (ENET_DMA_TX == direction){
-
- desc_tab = txdesc_tab;
- buf = &tx_buff[0][0];
- count = ENET_TXBUF_NUM;
- maxsize = ENET_TXBUF_SIZE;
-
-
- desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN;
-
-
- ENET_DMA_TDTADDR = (uint32_t)desc_tab;
- dma_current_txdesc = desc_tab;
- }else{
-
-
- desc_tab = rxdesc_tab;
- buf = &rx_buff[0][0];
- count = ENET_RXBUF_NUM;
- maxsize = ENET_RXBUF_SIZE;
-
-
- desc_status = ENET_RDES0_DAV;
-
- desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE;
-
-
- ENET_DMA_RDTADDR = (uint32_t)desc_tab;
- dma_current_rxdesc = desc_tab;
- }
-
-
- for(num = 0U; num < count; num++){
-
- desc = desc_tab + num;
-
- desc->status = desc_status;
- desc->control_buffer_size = desc_bufsize;
- desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
-
-
- if(num < (count - 1U)){
-
- desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U);
- }else{
-
-
- desc->buffer2_next_desc_addr = (uint32_t)desc_tab;
- }
- }
- }
- void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction)
- {
- uint32_t num = 0U, count = 0U, maxsize = 0U;
- uint32_t desc_status = 0U, desc_bufsize = 0U;
- enet_descriptors_struct *desc;
- enet_descriptors_struct *desc_tab;
- uint8_t *buf;
-
-
- ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL;
- ENET_DMA_BCTL |= DMA_BCTL_DPSL(0);
-
-
- if (ENET_DMA_TX == direction){
-
- desc_tab = txdesc_tab;
- buf = &tx_buff[0][0];
- count = ENET_TXBUF_NUM;
- maxsize = ENET_TXBUF_SIZE;
-
- desc_status = ENET_TDES0_TTSEN;
-
-
- ENET_DMA_TDTADDR = (uint32_t)desc_tab;
- dma_current_txdesc = desc_tab;
- }else{
-
-
- desc_tab = rxdesc_tab;
- buf = &rx_buff[0][0];
- count = ENET_RXBUF_NUM;
- maxsize = ENET_RXBUF_SIZE;
-
-
- desc_status = ENET_RDES0_DAV;
-
- desc_bufsize = ENET_RXBUF_SIZE;
-
-
- ENET_DMA_RDTADDR = (uint32_t)desc_tab;
- dma_current_rxdesc = desc_tab;
- }
-
-
- for(num=0U; num < count; num++){
-
- desc = desc_tab + num;
-
- desc->status = desc_status;
- desc->control_buffer_size = desc_bufsize;
- desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
-
-
- if(num == (count - 1U)){
- if (ENET_DMA_TX == direction){
-
- desc->status |= ENET_TDES0_TERM;
- }else{
-
- desc->control_buffer_size |= ENET_RDES1_RERM;
- }
- }
- }
- }
- ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[])
- {
- uint32_t offset = 0U, size = 0U;
- uint32_t timeout = 0U;
- uint32_t rdes0_tsv_flag;
-
-
- if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){
- return ERROR;
- }
-
-
- if(NULL != buffer){
-
- if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) &&
- ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) &&
- ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){
-
- size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U;
-
- if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){
- size = size + 4U;
- }
-
-
- if(size > bufsize){
- return ERROR;
- }
-
- for(offset = 0; offset < size; offset++){
- (*(buffer + offset)) = (*(__IO uint8_t *)((dma_current_rxdesc->buffer1_addr) + offset));
- }
- }else{
- return ERROR;
- }
- }
-
-
- if(NULL != timestamp){
-
- do{
- rdes0_tsv_flag = (dma_current_rxdesc->status & ENET_RDES0_TSV);
- timeout++;
- }while ((RESET == rdes0_tsv_flag) && (timeout < ENET_DELAY_TO));
-
-
- if(ENET_DELAY_TO == timeout){
- return ERROR;
- }
-
-
- dma_current_rxdesc->status &= ~ENET_RDES0_TSV;
-
- timestamp[0] = dma_current_rxdesc->timestamp_low;
- timestamp[1] = dma_current_rxdesc->timestamp_high;
- }
-
- dma_current_rxdesc->status = ENET_RDES0_DAV;
-
-
- if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){
-
- ENET_DMA_STAT = ENET_DMA_STAT_RBU;
-
- ENET_DMA_RPEN = 0;
- }
-
-
-
- if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
- dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr);
- }else{
-
- if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
-
- dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
- }else{
-
- dma_current_rxdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
- }
- }
-
- return SUCCESS;
- }
- ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[])
- {
- uint32_t offset = 0;
- uint32_t dma_tbu_flag, dma_tu_flag;
- uint32_t tdes0_ttmss_flag;
- uint32_t timeout = 0;
-
-
- if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){
- return ERROR;
- }
-
-
- if(length > ENET_MAX_FRAME_SIZE){
- return ERROR;
- }
-
- if(NULL != buffer){
-
- for(offset = 0; offset < length; offset++){
- (*(__IO uint8_t *)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset));
- }
- }
-
- dma_current_txdesc->control_buffer_size = length;
-
- dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG;
-
- dma_current_txdesc->status |= ENET_TDES0_DAV;
-
- dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU);
- dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU);
-
- if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){
-
- ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag);
-
- ENET_DMA_TPEN = 0;
- }
-
-
- if(NULL != timestamp){
-
- do{
- tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS);
- timeout++;
- }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO));
-
-
- if(ENET_DELAY_TO == timeout){
- return ERROR;
- }
-
-
- dma_current_txdesc->status &= ~ENET_TDES0_TTMSS;
-
- timestamp[0] = dma_current_txdesc->timestamp_low;
- timestamp[1] = dma_current_txdesc->timestamp_high;
- }
-
-
- if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){
- dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr);
- }else{
-
- if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){
-
- dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR);
- }else{
-
- dma_current_txdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
- }
- }
- return SUCCESS;
- }
- #else
- void enet_desc_select_normal_mode(void)
- {
- ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DFM;
- }
- void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab)
- {
- uint32_t num = 0U, count = 0U, maxsize = 0U;
- uint32_t desc_status = 0U, desc_bufsize = 0U;
- enet_descriptors_struct *desc, *desc_tab;
- uint8_t *buf;
-
- if(ENET_DMA_TX == direction){
-
- desc_tab = txdesc_tab;
- buf = &tx_buff[0][0];
- count = ENET_TXBUF_NUM;
- maxsize = ENET_TXBUF_SIZE;
-
- desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN;
-
- ENET_DMA_TDTADDR = (uint32_t)desc_tab;
- dma_current_txdesc = desc_tab;
- dma_current_ptp_txdesc = desc_ptptab;
- }else{
-
-
- desc_tab = rxdesc_tab;
- buf = &rx_buff[0][0];
- count = ENET_RXBUF_NUM;
- maxsize = ENET_RXBUF_SIZE;
-
- desc_status = ENET_RDES0_DAV;
-
- desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE;
-
- ENET_DMA_RDTADDR = (uint32_t)desc_tab;
- dma_current_rxdesc = desc_tab;
- dma_current_ptp_rxdesc = desc_ptptab;
- }
-
- for(num = 0U; num < count; num++){
-
- desc = desc_tab + num;
-
- desc->status = desc_status;
- desc->control_buffer_size = desc_bufsize;
- desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
-
-
- if(num < (count - 1U)){
-
- desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U);
- }else{
-
-
- desc->buffer2_next_desc_addr = (uint32_t)desc_tab;
- }
-
- (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr;
- (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr;
- }
-
- (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab;
- }
- void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab)
- {
- uint32_t num = 0U, count = 0U, maxsize = 0U;
- uint32_t desc_status = 0U, desc_bufsize = 0U;
- enet_descriptors_struct *desc, *desc_tab;
- uint8_t *buf;
-
- ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL;
- ENET_DMA_BCTL |= DMA_BCTL_DPSL(0);
-
- if(ENET_DMA_TX == direction){
-
- desc_tab = txdesc_tab;
- buf = &tx_buff[0][0];
- count = ENET_TXBUF_NUM;
- maxsize = ENET_TXBUF_SIZE;
-
- desc_status = ENET_TDES0_TTSEN;
-
- ENET_DMA_TDTADDR = (uint32_t)desc_tab;
- dma_current_txdesc = desc_tab;
- dma_current_ptp_txdesc = desc_ptptab;
- }else{
-
-
- desc_tab = rxdesc_tab;
- buf = &rx_buff[0][0];
- count = ENET_RXBUF_NUM;
- maxsize = ENET_RXBUF_SIZE;
-
- desc_status = ENET_RDES0_DAV;
-
- desc_bufsize = (uint32_t)ENET_RXBUF_SIZE;
-
- ENET_DMA_RDTADDR = (uint32_t)desc_tab;
- dma_current_rxdesc = desc_tab;
- dma_current_ptp_rxdesc = desc_ptptab;
- }
-
- for(num = 0U; num < count; num++){
-
- desc = desc_tab + num;
-
- desc->status = desc_status;
- desc->control_buffer_size = desc_bufsize;
- desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
-
- if(num == (count - 1U)){
- if (ENET_DMA_TX == direction){
-
- desc->status |= ENET_TDES0_TERM;
- }else{
-
- desc->control_buffer_size |= ENET_RDES1_RERM;
- }
- }
-
- (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr;
- (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr;
- }
-
- (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab;
- }
- ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[])
- {
- uint32_t offset = 0U, size = 0U;
-
- if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){
- return ERROR;
- }
-
- if(NULL != buffer){
-
- if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) &&
- ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) &&
- ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){
-
- size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U;
-
- if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){
- size = size + 4U;
- }
-
- if(size > bufsize){
- return ERROR;
- }
-
- for(offset = 0U; offset < size; offset++){
- (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset));
- }
- }else{
- return ERROR;
- }
- }
-
- timestamp[0] = dma_current_rxdesc->buffer1_addr;
- timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr;
- dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ;
- dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr;
-
- dma_current_rxdesc->status = ENET_RDES0_DAV;
-
-
- if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){
-
- ENET_DMA_STAT = ENET_DMA_STAT_RBU;
-
- ENET_DMA_RPEN = 0U;
- }
-
-
- if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
- dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr);
-
- if(0U != dma_current_ptp_rxdesc->status){
-
- dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
- }else{
-
- dma_current_ptp_rxdesc++;
- }
- }else{
-
- if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
-
- dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
-
- dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
- }else{
-
- dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
- dma_current_ptp_rxdesc ++;
- }
- }
- return SUCCESS;
- }
- ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[])
- {
- uint32_t offset = 0U, timeout = 0U;
- uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag;
-
- if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){
- return ERROR;
- }
-
- if(length > ENET_MAX_FRAME_SIZE){
- return ERROR;
- }
-
- if(NULL != buffer){
-
- for(offset = 0U; offset < length; offset++){
- (*(__IO uint8_t *) (uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset));
- }
- }
-
- dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF);
-
- dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG;
-
- dma_current_txdesc->status |= ENET_TDES0_DAV;
-
- dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU);
- dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU);
- if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){
-
- ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag);
-
- ENET_DMA_TPEN = 0U;
- }
-
- if(NULL != timestamp){
-
- do{
- tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS);
- timeout++;
- }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO));
-
- if(ENET_DELAY_TO == timeout){
- return ERROR;
- }
-
- dma_current_txdesc->status &= ~ENET_TDES0_TTMSS;
-
- timestamp[0] = dma_current_txdesc->buffer1_addr;
- timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr;
- }
- dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ;
- dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr;
-
-
- if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){
- dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr);
-
- if(0U != dma_current_ptp_txdesc->status){
-
- dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status);
- }else{
-
- dma_current_ptp_txdesc++;
- }
- }else{
-
- if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){
-
- dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR);
-
- dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status);
- }else{
-
- dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
- dma_current_ptp_txdesc ++;
- }
- }
- return SUCCESS;
- }
- #endif
- void enet_wum_filter_register_pointer_reset(void)
- {
- ENET_MAC_WUM |= ENET_MAC_WUM_WUFFRPR;
- }
- void enet_wum_filter_config(uint32_t pdata[])
- {
- uint32_t num = 0U;
-
- for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){
- ENET_MAC_RWFF = pdata[num];
- }
- }
- void enet_wum_feature_enable(uint32_t feature)
- {
- ENET_MAC_WUM |= feature;
- }
- void enet_wum_feature_disable(uint32_t feature)
- {
- ENET_MAC_WUM &= (~feature);
- }
- void enet_msc_counters_reset(void)
- {
-
- ENET_MSC_CTL |= ENET_MSC_CTL_CTR;
- }
- void enet_msc_feature_enable(uint32_t feature)
- {
- ENET_MSC_CTL |= feature;
- }
- void enet_msc_feature_disable(uint32_t feature)
- {
- ENET_MSC_CTL &= (~feature);
- }
- void enet_msc_counters_preset_config(enet_msc_preset_enum mode)
- {
- ENET_MSC_CTL &= ENET_MSC_PRESET_MASK;
- ENET_MSC_CTL |= (uint32_t)mode;
- }
- uint32_t enet_msc_counters_get(enet_msc_counter_enum counter)
- {
- uint32_t reval;
- reval = REG32((ENET + (uint32_t)counter));
- return reval;
- }
- uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond)
- {
- uint64_t val = subsecond * 1000000000Ull;
- val >>= 31;
- return (uint32_t)val;
- }
- uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond)
- {
- uint64_t val = nanosecond * 0x80000000Ull;
- val /= 1000000000U;
- return (uint32_t)val;
- }
- void enet_ptp_feature_enable(uint32_t feature)
- {
- ENET_PTP_TSCTL |= feature;
- }
- void enet_ptp_feature_disable(uint32_t feature)
- {
- ENET_PTP_TSCTL &= ~feature;
- }
- ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func)
- {
- uint32_t temp_config = 0U, temp_state = 0U;
- uint32_t timeout = 0U;
- ErrStatus enet_state = SUCCESS;
- switch(func){
- case ENET_CKNT_ORDINARY:
- case ENET_CKNT_BOUNDARY:
- case ENET_CKNT_END_TO_END:
- case ENET_CKNT_PEER_TO_PEER:
- ENET_PTP_TSCTL &= ~ENET_PTP_TSCTL_CKNT;
- ENET_PTP_TSCTL |= (uint32_t)func;
- break;
- case ENET_PTP_ADDEND_UPDATE:
-
- do{
- temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU;
- timeout++;
- }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
-
- if(ENET_DELAY_TO == timeout){
- enet_state = ERROR;
- }else{
- ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU;
- }
- break;
- case ENET_PTP_SYSTIME_UPDATE:
-
- do{
- temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI);
- timeout++;
- }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
-
- if(ENET_DELAY_TO == timeout){
- enet_state = ERROR;
- }else{
- ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU;
- }
- break;
- case ENET_PTP_SYSTIME_INIT:
-
- do{
- temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI;
- timeout++;
- }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
-
- if(ENET_DELAY_TO == timeout){
- enet_state = ERROR;
- }else{
- ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI;
- }
- break;
- default:
- temp_config = (uint32_t)func & (~BIT(31));
- if(RESET != ((uint32_t)func & BIT(31))){
- ENET_PTP_TSCTL |= temp_config;
- }else{
- ENET_PTP_TSCTL &= ~temp_config;
- }
- break;
- }
- return enet_state;
- }
- void enet_ptp_subsecond_increment_config(uint32_t subsecond)
- {
- ENET_PTP_SSINC = PTP_SSINC_STMSSI(subsecond);
- }
- void enet_ptp_timestamp_addend_config(uint32_t add)
- {
- ENET_PTP_TSADDEND = add;
- }
- void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond)
- {
- ENET_PTP_TSUH = second;
- ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond);
- }
- void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond)
- {
- ENET_PTP_ETH = second;
- ENET_PTP_ETL = nanosecond;
- }
- void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct)
- {
- uint32_t temp_sec = 0U, temp_subs = 0U;
-
- temp_sec = (uint32_t)ENET_PTP_TSH;
- temp_subs = (uint32_t)ENET_PTP_TSL;
-
-
- systime_struct->second = temp_sec;
- systime_struct->nanosecond = GET_PTP_TSL_STMSS(temp_subs);
- systime_struct->nanosecond = enet_ptp_subsecond_2_nanosecond(systime_struct->nanosecond);
- systime_struct->sign = GET_PTP_TSL_STS(temp_subs);
- }
- void enet_ptp_pps_output_frequency_config(uint32_t freq)
- {
- ENET_PTP_PPSCTL = freq;
- }
- void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg)
- {
-
- enet_interrupt_disable(ENET_MAC_INT_TMSTIM);
-
- enet_ptp_feature_enable(ENET_ALL_RX_TIMESTAMP | ENET_RXTX_TIMESTAMP);
-
- enet_ptp_subsecond_increment_config(accuracy_cfg);
- if(ENET_PTP_FINEMODE == updatemethod){
-
- enet_ptp_timestamp_addend_config(carry_cfg);
- enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
-
- while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_ADDEND_UPDATE)){
- }
- }
-
- enet_ptp_timestamp_function_config((enet_ptp_function_enum)updatemethod);
-
- enet_ptp_timestamp_update_config(ENET_PTP_ADD_TO_TIME, init_sec, init_subsec);
- enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT);
- #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE
- enet_desc_select_enhanced_mode();
- #endif
- }
- void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg)
- {
-
- enet_ptp_timestamp_addend_config((uint32_t)carry_cfg);
- enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
- }
- void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct)
- {
- uint32_t subsecond_val;
- uint32_t carry_cfg;
- subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond);
-
- carry_cfg = ENET_PTP_TSADDEND_TMSA;
-
- enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val);
- enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_UPDATE);
-
- while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_UPDATE)){
- }
-
- enet_ptp_timestamp_addend_config(carry_cfg);
- enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
- }
- void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct)
- {
- uint32_t subsecond_val;
- subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond);
-
- enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val);
- enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT);
-
-
- while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_INIT)){
- }
- }
- FlagStatus enet_ptp_flag_get(uint32_t flag)
- {
- FlagStatus bitstatus = RESET;
- if ((uint32_t)RESET != (ENET_PTP_TSCTL & flag)){
- bitstatus = SET;
- }
- return bitstatus;
- }
- void enet_initpara_reset(void)
- {
- enet_initpara.option_enable = 0U;
- enet_initpara.forward_frame = 0U;
- enet_initpara.dmabus_mode = 0U;
- enet_initpara.dma_maxburst = 0U;
- enet_initpara.dma_arbitration = 0U;
- enet_initpara.store_forward_mode = 0U;
- enet_initpara.dma_function = 0U;
- enet_initpara.vlan_config = 0U;
- enet_initpara.flow_control = 0U;
- enet_initpara.hashtable_high = 0U;
- enet_initpara.hashtable_low = 0U;
- enet_initpara.framesfilter_mode = 0U;
- enet_initpara.halfduplex_param = 0U;
- enet_initpara.timer_config = 0U;
- enet_initpara.interframegap = 0U;
- }
- static void enet_default_init(void)
- {
- uint32_t reg_value = 0U;
-
-
- reg_value = ENET_MAC_CFG;
- reg_value &= MAC_CFG_MASK;
- reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \
- | ENET_SPEEDMODE_10M |ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \
- | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \
- | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \
- | ENET_DEFERRALCHECK_DISABLE \
- | ENET_TYPEFRAME_CRC_DROP_DISABLE \
- | ENET_AUTO_PADCRC_DROP_DISABLE \
- | ENET_CHECKSUMOFFLOAD_DISABLE;
- ENET_MAC_CFG = reg_value;
-
- ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE |ENET_DEST_FILTER_INVERSE_DISABLE \
- |ENET_MULTICAST_FILTER_PERFECT |ENET_UNICAST_FILTER_PERFECT \
- |ENET_PCFRM_PREVENT_ALL |ENET_BROADCASTFRAMES_ENABLE \
- |ENET_PROMISCUOUS_DISABLE |ENET_RX_FILTER_ENABLE;
-
- ENET_MAC_HLH = 0x0U;
- ENET_MAC_HLL = 0x0U;
-
- reg_value = ENET_MAC_FCTL;
- reg_value &= MAC_FCTL_MASK;
- reg_value |= MAC_FCTL_PTM(0) |ENET_ZERO_QUANTA_PAUSE_DISABLE \
- |ENET_PAUSETIME_MINUS4 |ENET_UNIQUE_PAUSEDETECT \
- |ENET_RX_FLOWCONTROL_DISABLE |ENET_TX_FLOWCONTROL_DISABLE;
- ENET_MAC_FCTL = reg_value;
-
- ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT |MAC_VLT_VLTI(0);
-
-
- reg_value = ENET_DMA_CTL;
- reg_value &= DMA_CTL_MASK;
- reg_value |= ENET_TCPIP_CKSUMERROR_DROP |ENET_RX_MODE_STOREFORWARD \
- |ENET_FLUSH_RXFRAME_ENABLE |ENET_TX_MODE_STOREFORWARD \
- |ENET_TX_THRESHOLD_64BYTES |ENET_RX_THRESHOLD_64BYTES \
- |ENET_SECONDFRAME_OPT_DISABLE;
- ENET_DMA_CTL = reg_value;
-
- reg_value = ENET_DMA_BCTL;
- reg_value &= DMA_BCTL_MASK;
- reg_value = ENET_ADDRESS_ALIGN_ENABLE |ENET_ARBITRATION_RXTX_2_1 \
- |ENET_RXDP_32BEAT |ENET_PGBL_32BEAT |ENET_RXTX_DIFFERENT_PGBL \
- |ENET_FIXED_BURST_ENABLE |ENET_MIXED_BURST_DISABLE \
- |ENET_NORMAL_DESCRIPTOR;
- ENET_DMA_BCTL = reg_value;
- }
- #ifndef USE_DELAY
- static void enet_delay(uint32_t ncount)
- {
- __IO uint32_t delay_time = 0U;
- for(delay_time = ncount; delay_time != 0U; delay_time--){
- }
- }
- #endif
- #endif
|