1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702 |
- #ifndef GD32F30X_ENET_H
- #define GD32F30X_ENET_H
- #include "gd32f30x.h"
- #define IF_USE_EXTERNPHY_LIB 0
- #if (1 == IF_USE_EXTERNPHY_LIB)
- #include "phy.h"
- #endif
- #ifndef ENET_RXBUF_NUM
- #define ENET_RXBUF_NUM 5U
- #endif
- #ifndef ENET_TXBUF_NUM
- #define ENET_TXBUF_NUM 5U
- #endif
- #ifndef ENET_RXBUF_SIZE
- #define ENET_RXBUF_SIZE ENET_MAX_FRAME_SIZE
- #endif
- #ifndef ENET_TXBUF_SIZE
- #define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE
- #endif
- #ifndef _PHY_H_
- #define DP83848 0
- #define LAN8700 1
- #define PHY_TYPE DP83848
- #define PHY_ADDRESS ((uint16_t)1U)
-
- #define PHY_READ_TO ((uint32_t)0x0004FFFFU)
- #define PHY_WRITE_TO ((uint32_t)0x0004FFFFU)
- #define PHY_RESETDELAY ((uint32_t)0x008FFFFFU)
- #define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU)
-
- #define PHY_REG_BCR 0U
- #define PHY_REG_BSR 1U
- #define PHY_RESET ((uint16_t)0x8000)
- #define PHY_LOOPBACK ((uint16_t)0x4000)
- #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100)
- #define PHY_HALFDUPLEX_100M ((uint16_t)0x2000)
- #define PHY_FULLDUPLEX_10M ((uint16_t)0x0100)
- #define PHY_HALFDUPLEX_10M ((uint16_t)0x0000)
- #define PHY_AUTONEGOTIATION ((uint16_t)0x1000)
- #define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200)
- #define PHY_POWERDOWN ((uint16_t)0x0800)
- #define PHY_ISOLATE ((uint16_t)0x0400)
- #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020)
- #define PHY_LINKED_STATUS ((uint16_t)0x0004)
- #define PHY_JABBER_DETECTION ((uint16_t)0x0002)
- #if(PHY_TYPE == LAN8700)
- #define PHY_SR 31U
- #define PHY_SPEED_STATUS ((uint16_t)0x0004)
- #define PHY_DUPLEX_STATUS ((uint16_t)0x0010)
- #elif(PHY_TYPE == DP83848)
- #define PHY_SR 16U
- #define PHY_SPEED_STATUS ((uint16_t)0x0002)
- #define PHY_DUPLEX_STATUS ((uint16_t)0x0004)
- #endif
- #endif
- #define ENET ENET_BASE
- #define ENET_MAC_CFG REG32((ENET) + 0x00U)
- #define ENET_MAC_FRMF REG32((ENET) + 0x04U)
- #define ENET_MAC_HLH REG32((ENET) + 0x08U)
- #define ENET_MAC_HLL REG32((ENET) + 0x0CU)
- #define ENET_MAC_PHY_CTL REG32((ENET) + 0x10U)
- #define ENET_MAC_PHY_DATA REG32((ENET) + 0x14U)
- #define ENET_MAC_FCTL REG32((ENET) + 0x18U)
- #define ENET_MAC_VLT REG32((ENET) + 0x1CU)
- #define ENET_MAC_RWFF REG32((ENET) + 0x28U)
- #define ENET_MAC_WUM REG32((ENET) + 0x2CU)
- #define ENET_MAC_DBG REG32((ENET) + 0x34U)
- #define ENET_MAC_INTF REG32((ENET) + 0x38U)
- #define ENET_MAC_INTMSK REG32((ENET) + 0x3CU)
- #define ENET_MAC_ADDR0H REG32((ENET) + 0x40U)
- #define ENET_MAC_ADDR0L REG32((ENET) + 0x44U)
- #define ENET_MAC_ADDR1H REG32((ENET) + 0x48U)
- #define ENET_MAC_ADDR1L REG32((ENET) + 0x4CU)
- #define ENET_MAC_ADDT2H REG32((ENET) + 0x50U)
- #define ENET_MAC_ADDR2L REG32((ENET) + 0x54U)
- #define ENET_MAC_ADDR3H REG32((ENET) + 0x58U)
- #define ENET_MAC_ADDR3L REG32((ENET) + 0x5CU)
- #define ENET_MAC_FCTH REG32((ENET) + 0x1080U)
- #define ENET_MSC_CTL REG32((ENET) + 0x100U)
- #define ENET_MSC_RINTF REG32((ENET) + 0x104U)
- #define ENET_MSC_TINTF REG32((ENET) + 0x108U)
- #define ENET_MSC_RINTMSK REG32((ENET) + 0x10CU)
- #define ENET_MSC_TINTMSK REG32((ENET) + 0x110U)
- #define ENET_MSC_SCCNT REG32((ENET) + 0x14CU)
- #define ENET_MSC_MSCCNT REG32((ENET) + 0x150U)
- #define ENET_MSC_TGFCNT REG32((ENET) + 0x168U)
- #define ENET_MSC_RFCECNT REG32((ENET) + 0x194U)
- #define ENET_MSC_RFAECNT REG32((ENET) + 0x198U)
- #define ENET_MSC_RGUFCNT REG32((ENET) + 0x1C4U)
- #define ENET_PTP_TSCTL REG32((ENET) + 0x700U)
- #define ENET_PTP_SSINC REG32((ENET) + 0x704U)
- #define ENET_PTP_TSH REG32((ENET) + 0x708U)
- #define ENET_PTP_TSL REG32((ENET) + 0x70CU)
- #define ENET_PTP_TSUH REG32((ENET) + 0x710U)
- #define ENET_PTP_TSUL REG32((ENET) + 0x714U)
- #define ENET_PTP_TSADDEND REG32((ENET) + 0x718U)
- #define ENET_PTP_ETH REG32((ENET) + 0x71CU)
- #define ENET_PTP_ETL REG32((ENET) + 0x720U)
- #define ENET_PTP_TSF REG32((ENET) + 0x728U)
- #define ENET_PTP_PPSCTL REG32((ENET) + 0x72CU)
- #define ENET_DMA_BCTL REG32((ENET) + 0x1000U)
- #define ENET_DMA_TPEN REG32((ENET) + 0x1004U)
- #define ENET_DMA_RPEN REG32((ENET) + 0x1008U)
- #define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU)
- #define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U)
- #define ENET_DMA_STAT REG32((ENET) + 0x1014U)
- #define ENET_DMA_CTL REG32((ENET) + 0x1018U)
- #define ENET_DMA_INTEN REG32((ENET) + 0x101CU)
- #define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U)
- #define ENET_DMA_RSWDC REG32((ENET) + 0x1024U)
- #define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U)
- #define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU)
- #define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U)
- #define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U)
- #define ENET_MAC_CFG_REN BIT(2)
- #define ENET_MAC_CFG_TEN BIT(3)
- #define ENET_MAC_CFG_DFC BIT(4)
- #define ENET_MAC_CFG_BOL BITS(5,6)
- #define ENET_MAC_CFG_APCD BIT(7)
- #define ENET_MAC_CFG_RTD BIT(9)
- #define ENET_MAC_CFG_IPFCO BIT(10)
- #define ENET_MAC_CFG_DPM BIT(11)
- #define ENET_MAC_CFG_LBM BIT(12)
- #define ENET_MAC_CFG_ROD BIT(13)
- #define ENET_MAC_CFG_SPD BIT(14)
- #define ENET_MAC_CFG_CSD BIT(16)
- #define ENET_MAC_CFG_IGBS BITS(17,19)
- #define ENET_MAC_CFG_JBD BIT(22)
- #define ENET_MAC_CFG_WDD BIT(23)
- #define ENET_MAC_CFG_TFCD BIT(25)
- #define ENET_MAC_FRMF_PM BIT(0)
- #define ENET_MAC_FRMF_HUF BIT(1)
- #define ENET_MAC_FRMF_HMF BIT(2)
- #define ENET_MAC_FRMF_DAIFLT BIT(3)
- #define ENET_MAC_FRMF_MFD BIT(4)
- #define ENET_MAC_FRMF_BFRMD BIT(5)
- #define ENET_MAC_FRMF_PCFRM BITS(6,7)
- #define ENET_MAC_FRMF_SAIFLT BIT(8)
- #define ENET_MAC_FRMF_SAFLT BIT(9)
- #define ENET_MAC_FRMF_HPFLT BIT(10)
- #define ENET_MAC_FRMF_FAR BIT(31)
-
- #define ENET_MAC_HLH_HLH BITS(0,31)
-
- #define ENET_MAC_HLL_HLL BITS(0,31)
-
- #define ENET_MAC_PHY_CTL_PB BIT(0)
- #define ENET_MAC_PHY_CTL_PW BIT(1)
- #define ENET_MAC_PHY_CTL_CLR BITS(2,4)
- #define ENET_MAC_PHY_CTL_PR BITS(6,10)
- #define ENET_MAC_PHY_CTL_PA BITS(11,15)
-
- #define ENET_MAC_PHY_DATA_PD BITS(0,15)
-
- #define ENET_MAC_FCTL_FLCBBKPA BIT(0)
- #define ENET_MAC_FCTL_TFCEN BIT(1)
- #define ENET_MAC_FCTL_RFCEN BIT(2)
- #define ENET_MAC_FCTL_UPFDT BIT(3)
- #define ENET_MAC_FCTL_PLTS BITS(4,5)
- #define ENET_MAC_FCTL_DZQP BIT(7)
- #define ENET_MAC_FCTL_PTM BITS(16,31)
-
- #define ENET_MAC_VLT_VLTI BITS(0,15)
- #define ENET_MAC_VLT_VLTC BIT(16)
-
- #define ENET_MAC_RWFF_DATA BITS(0,31)
-
-
- #define ENET_MAC_WUM_PWD BIT(0)
- #define ENET_MAC_WUM_MPEN BIT(1)
- #define ENET_MAC_WUM_WFEN BIT(2)
- #define ENET_MAC_WUM_MPKR BIT(5)
- #define ENET_MAC_WUM_WUFR BIT(6)
- #define ENET_MAC_WUM_GU BIT(9)
- #define ENET_MAC_WUM_WUFFRPR BIT(31)
-
- #define ENET_MAC_DBG_MRNI BIT(0)
- #define ENET_MAC_DBG_RXAFS BITS(1,2)
- #define ENET_MAC_DBG_RXFW BIT(4)
- #define ENET_MAC_DBG_RXFRS BITS(5,6)
- #define ENET_MAC_DBG_RXFS BITS(8,9)
- #define ENET_MAC_DBG_MTNI BIT(16)
- #define ENET_MAC_DBG_SOMT BITS(17,18)
- #define ENET_MAC_DBG_PCS BIT(19)
- #define ENET_MAC_DBG_TXFRS BITS(20,21)
- #define ENET_MAC_DBG_TXFW BIT(22)
- #define ENET_MAC_DBG_TXFNE BIT(24)
- #define ENET_MAC_DBG_TXFF BIT(25)
-
- #define ENET_MAC_INTF_WUM BIT(3)
- #define ENET_MAC_INTF_MSC BIT(4)
- #define ENET_MAC_INTF_MSCR BIT(5)
- #define ENET_MAC_INTF_MSCT BIT(6)
- #define ENET_MAC_INTF_TMST BIT(9)
- #define ENET_MAC_INTMSK_WUMIM BIT(3)
- #define ENET_MAC_INTMSK_TMSTIM BIT(9)
- #define ENET_MAC_ADDR0H_ADDR0H BITS(0,15)
- #define ENET_MAC_ADDR0H_MO BIT(31)
-
- #define ENET_MAC_ADDR0L_ADDR0L BITS(0,31)
-
- #define ENET_MAC_ADDR1H_ADDR1H BITS(0,15)
- #define ENET_MAC_ADDR1H_MB BITS(24,29)
- #define ENET_MAC_ADDR1H_SAF BIT(30)
- #define ENET_MAC_ADDR1H_AFE BIT(31)
-
- #define ENET_MAC_ADDR1L_ADDR1L BITS(0,31)
-
- #define ENET_MAC_ADDR2H_ADDR2H BITS(0,15)
- #define ENET_MAC_ADDR2H_MB BITS(24,29)
- #define ENET_MAC_ADDR2H_SAF BIT(30)
- #define ENET_MAC_ADDR2H_AFE BIT(31)
-
- #define ENET_MAC_ADDR2L_ADDR2L BITS(0,31)
-
- #define ENET_MAC_ADDR3H_ADDR3H BITS(0,15)
- #define ENET_MAC_ADDR3H_MB BITS(24,29)
- #define ENET_MAC_ADDR3H_SAF BIT(30)
- #define ENET_MAC_ADDR3H_AFE BIT(31)
- #define ENET_MAC_ADDR3L_ADDR3L BITS(0,31)
-
- #define ENET_MAC_FCTH_RFA BITS(0,2)
- #define ENET_MAC_FCTH_RFD BITS(4,6)
-
- #define ENET_MSC_CTL_CTR BIT(0)
- #define ENET_MSC_CTL_CTSR BIT(1)
- #define ENET_MSC_CTL_RTOR BIT(2)
- #define ENET_MSC_CTL_MCFZ BIT(3)
- #define ENET_MSC_CTL_PMC BIT(4)
- #define ENET_MSC_CTL_AFHPM BIT(5)
- #define ENET_MSC_RINTF_RFCE BIT(5)
- #define ENET_MSC_RINTF_RFAE BIT(6)
- #define ENET_MSC_RINTF_RGUF BIT(17)
-
- #define ENET_MSC_TINTF_TGFSC BIT(14)
- #define ENET_MSC_TINTF_TGFMSC BIT(15)
- #define ENET_MSC_TINTF_TGF BIT(21)
- #define ENET_MSC_RINTMSK_RFCEIM BIT(5)
- #define ENET_MSC_RINTMSK_RFAEIM BIT(6)
- #define ENET_MSC_RINTMSK_RGUFIM BIT(17)
-
- #define ENET_MSC_TINTMSK_TGFSCIM BIT(14)
- #define ENET_MSC_TINTMSK_TGFMSCIM BIT(15)
- #define ENET_MSC_TINTMSK_TGFIM BIT(21)
-
- #define ENET_MSC_SCCNT_SCC BITS(0,31)
-
- #define ENET_MSC_MSCCNT_MSCC BITS(0,31)
-
- #define ENET_MSC_TGFCNT_TGF BITS(0,31)
-
- #define ENET_MSC_RFCECNT_RFCER BITS(0,31)
-
- #define ENET_MSC_RFAECNT_RFAER BITS(0,31)
-
- #define ENET_MSC_RGUFCNT_RGUF BITS(0,31)
-
- #define ENET_PTP_TSCTL_TMSEN BIT(0)
- #define ENET_PTP_TSCTL_TMSFCU BIT(1)
- #define ENET_PTP_TSCTL_TMSSTI BIT(2)
- #define ENET_PTP_TSCTL_TMSSTU BIT(3)
- #define ENET_PTP_TSCTL_TMSITEN BIT(4)
- #define ENET_PTP_TSCTL_TMSARU BIT(5)
- #define ENET_PTP_TSCTL_ARFSEN BIT(8)
- #define ENET_PTP_TSCTL_SCROM BIT(9)
- #define ENET_PTP_TSCTL_PFSV BIT(10)
- #define ENET_PTP_TSCTL_ESEN BIT(11)
- #define ENET_PTP_TSCTL_IP6SEN BIT(12)
- #define ENET_PTP_TSCTL_IP4SEN BIT(13)
- #define ENET_PTP_TSCTL_ETMSEN BIT(14)
- #define ENET_PTP_TSCTL_MNMSEN BIT(15)
- #define ENET_PTP_TSCTL_CKNT BITS(16,17)
- #define ENET_PTP_TSCTL_MAFEN BIT(18)
-
- #define ENET_PTP_SSINC_STMSSI BITS(0,7)
-
- #define ENET_PTP_TSH_STMS BITS(0,31)
-
- #define ENET_PTP_TSL_STMSS BITS(0,30)
- #define ENET_PTP_TSL_STS BIT(31)
-
- #define ENET_PTP_TSUH_TMSUS BITS(0,31)
-
- #define ENET_PTP_TSUL_TMSUSS BITS(0,30)
- #define ENET_PTP_TSUL_TMSUPNS BIT(31)
- #define ENET_PTP_TSADDEND_TMSA BITS(0,31)
-
- #define ENET_PTP_ETH_ETSH BITS(0,31)
-
- #define ENET_PTP_ETL_ETSL BITS(0,31)
-
- #define ENET_PTP_TSF_TSSCO BIT(0)
- #define ENET_PTP_TSF_TTM BIT(1)
-
- #define ENET_PTP_PPSCTL_PPSOFC BITS(0,3)
- #define ENET_DMA_BCTL_SWR BIT(0)
- #define ENET_DMA_BCTL_DAB BIT(1)
- #define ENET_DMA_BCTL_DPSL BITS(2,6)
- #define ENET_DMA_BCTL_DFM BIT(7)
- #define ENET_DMA_BCTL_PGBL BITS(8,13)
- #define ENET_DMA_BCTL_RTPR BITS(14,15)
- #define ENET_DMA_BCTL_FB BIT(16)
- #define ENET_DMA_BCTL_RXDP BITS(17,22)
- #define ENET_DMA_BCTL_UIP BIT(23)
- #define ENET_DMA_BCTL_FPBL BIT(24)
- #define ENET_DMA_BCTL_AA BIT(25)
- #define ENET_DMA_BCTL_MB BIT(26)
-
- #define ENET_DMA_TPEN_TPE BITS(0,31)
-
- #define ENET_DMA_RPEN_RPE BITS(0,31)
- #define ENET_DMA_RDTADDR_SRT BITS(0,31)
-
- #define ENET_DMA_TDTADDR_STT BITS(0,31)
-
- #define ENET_DMA_STAT_TS BIT(0)
- #define ENET_DMA_STAT_TPS BIT(1)
- #define ENET_DMA_STAT_TBU BIT(2)
- #define ENET_DMA_STAT_TJT BIT(3)
- #define ENET_DMA_STAT_RO BIT(4)
- #define ENET_DMA_STAT_TU BIT(5)
- #define ENET_DMA_STAT_RS BIT(6)
- #define ENET_DMA_STAT_RBU BIT(7)
- #define ENET_DMA_STAT_RPS BIT(8)
- #define ENET_DMA_STAT_RWT BIT(9)
- #define ENET_DMA_STAT_ET BIT(10)
- #define ENET_DMA_STAT_FBE BIT(13)
- #define ENET_DMA_STAT_ER BIT(14)
- #define ENET_DMA_STAT_AI BIT(15)
- #define ENET_DMA_STAT_NI BIT(16)
- #define ENET_DMA_STAT_RP BITS(17,19)
- #define ENET_DMA_STAT_TP BITS(20,22)
- #define ENET_DMA_STAT_EB BITS(23,25)
- #define ENET_DMA_STAT_MSC BIT(27)
- #define ENET_DMA_STAT_WUM BIT(28)
- #define ENET_DMA_STAT_TST BIT(29)
-
- #define ENET_DMA_CTL_SRE BIT(1)
- #define ENET_DMA_CTL_OSF BIT(2)
- #define ENET_DMA_CTL_RTHC BITS(3,4)
- #define ENET_DMA_CTL_FUF BIT(6)
- #define ENET_DMA_CTL_FERF BIT(7)
- #define ENET_DMA_CTL_STE BIT(13)
- #define ENET_DMA_CTL_TTHC BITS(14,16)
- #define ENET_DMA_CTL_FTF BIT(20)
- #define ENET_DMA_CTL_TSFD BIT(21)
- #define ENET_DMA_CTL_DAFRF BIT(24)
- #define ENET_DMA_CTL_RSFD BIT(25)
- #define ENET_DMA_CTL_DTCERFD BIT(26)
-
- #define ENET_DMA_INTEN_TIE BIT(0)
- #define ENET_DMA_INTEN_TPSIE BIT(1)
- #define ENET_DMA_INTEN_TBUIE BIT(2)
- #define ENET_DMA_INTEN_TJTIE BIT(3)
- #define ENET_DMA_INTEN_ROIE BIT(4)
- #define ENET_DMA_INTEN_TUIE BIT(5)
- #define ENET_DMA_INTEN_RIE BIT(6)
- #define ENET_DMA_INTEN_RBUIE BIT(7)
- #define ENET_DMA_INTEN_RPSIE BIT(8)
- #define ENET_DMA_INTEN_RWTIE BIT(9)
- #define ENET_DMA_INTEN_ETIE BIT(10)
- #define ENET_DMA_INTEN_FBEIE BIT(13)
- #define ENET_DMA_INTEN_ERIE BIT(14)
- #define ENET_DMA_INTEN_AIE BIT(15)
- #define ENET_DMA_INTEN_NIE BIT(16)
-
- #define ENET_DMA_MFBOCNT_MSFC BITS(0,15)
- #define ENET_DMA_MFBOCNT_MSFA BITS(17,27)
- #define ENET_DMA_RSWDC_WDCFRS BITS(0,7)
- #define ENET_DMA_CTDADDR_TDAP BITS(0,31)
- #define ENET_DMA_CRDADDR_RDAP BITS(0,31)
-
- #define ENET_DMA_CTBADDR_TBAP BITS(0,31)
-
- #define ENET_DMA_CRBADDR_RBAP BITS(0,31)
- #define ENET_TDES0_DB BIT(0)
- #define ENET_TDES0_UFE BIT(1)
- #define ENET_TDES0_EXD BIT(2)
- #define ENET_TDES0_COCNT BITS(3,6)
- #define ENET_TDES0_VFRM BIT(7)
- #define ENET_TDES0_ECO BIT(8)
- #define ENET_TDES0_LCO BIT(9)
- #define ENET_TDES0_NCA BIT(10)
- #define ENET_TDES0_LCA BIT(11)
- #define ENET_TDES0_IPPE BIT(12)
- #define ENET_TDES0_FRMF BIT(13)
- #define ENET_TDES0_JT BIT(14)
- #define ENET_TDES0_ES BIT(15)
- #define ENET_TDES0_IPHE BIT(16)
- #define ENET_TDES0_TTMSS BIT(17)
- #define ENET_TDES0_TCHM BIT(20)
- #define ENET_TDES0_TERM BIT(21)
- #define ENET_TDES0_CM BITS(22,23)
- #define ENET_TDES0_TTSEN BIT(25)
- #define ENET_TDES0_DPAD BIT(26)
- #define ENET_TDES0_DCRC BIT(27)
- #define ENET_TDES0_FSG BIT(28)
- #define ENET_TDES0_LSG BIT(29)
- #define ENET_TDES0_INTC BIT(30)
- #define ENET_TDES0_DAV BIT(31)
- #define ENET_TDES1_TB1S BITS(0,12)
- #define ENET_TDES1_TB2S BITS(16,28)
- #define ENET_TDES2_TB1AP BITS(0,31)
- #define ENET_TDES3_TB2AP BITS(0,31)
- #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE
- #define ENET_TDES6_TTSL BITS(0,31)
- #define ENET_TDES7_TTSH BITS(0,31)
- #endif
- #define ENET_RDES0_PCERR BIT(0)
- #define ENET_RDES0_EXSV BIT(0)
- #define ENET_RDES0_CERR BIT(1)
- #define ENET_RDES0_DBERR BIT(2)
- #define ENET_RDES0_RERR BIT(3)
- #define ENET_RDES0_RWDT BIT(4)
- #define ENET_RDES0_FRMT BIT(5)
- #define ENET_RDES0_LCO BIT(6)
- #define ENET_RDES0_IPHERR BIT(7)
- #define ENET_RDES0_TSV BIT(7)
- #define ENET_RDES0_LDES BIT(8)
- #define ENET_RDES0_FDES BIT(9)
- #define ENET_RDES0_VTAG BIT(10)
- #define ENET_RDES0_OERR BIT(11)
- #define ENET_RDES0_LERR BIT(12)
- #define ENET_RDES0_SAFF BIT(13)
- #define ENET_RDES0_DERR BIT(14)
- #define ENET_RDES0_ERRS BIT(15)
- #define ENET_RDES0_FRML BITS(16,29)
- #define ENET_RDES0_DAFF BIT(30)
- #define ENET_RDES0_DAV BIT(31)
-
- #define ENET_RDES1_RB1S BITS(0,12)
- #define ENET_RDES1_RCHM BIT(14)
- #define ENET_RDES1_RERM BIT(15)
- #define ENET_RDES1_RB2S BITS(16,28)
- #define ENET_RDES1_DINTC BIT(31)
- #define ENET_RDES2_RB1AP BITS(0,31)
- #define ENET_RDES3_RB2AP BITS(0,31)
- #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE
- #define ENET_RDES4_IPPLDT BITS(0,2)
- #define ENET_RDES4_IPHERR BIT(3)
- #define ENET_RDES4_IPPLDERR BIT(4)
- #define ENET_RDES4_IPCKSB BIT(5)
- #define ENET_RDES4_IPF4 BIT(6)
- #define ENET_RDES4_IPF6 BIT(7)
- #define ENET_RDES4_PTPMT BITS(8,11)
- #define ENET_RDES4_PTPOEF BIT(12)
- #define ENET_RDES4_PTPVF BIT(13)
- #define ENET_RDES6_RTSL BITS(0,31)
- #define ENET_RDES7_RTSH BITS(0,31)
- #endif
- #define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
- #define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph)>>6)))
- #define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
- #define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m)))
- #define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4])
- #define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0])
- #define ENET_ADDRH_BASE ((ENET) + 0x40U)
- #define ENET_ADDRL_BASE ((ENET) + 0x44U)
- #define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU))
- #define MAC_FCTL_REG_OFFSET 0x0018U
- #define MAC_WUM_REG_OFFSET 0x002CU
- #define MAC_INTF_REG_OFFSET 0x0038U
- #define MAC_INTMSK_REG_OFFSET 0x003CU
- #define MSC_RINTF_REG_OFFSET 0x0104U
- #define MSC_TINTF_REG_OFFSET 0x0108U
- #define MSC_RINTMSK_REG_OFFSET 0x010CU
- #define MSC_TINTMSK_REG_OFFSET 0x0110U
- #define MSC_SCCNT_REG_OFFSET 0x014CU
- #define MSC_MSCCNT_REG_OFFSET 0x0150U
- #define MSC_TGFCNT_REG_OFFSET 0x0168U
- #define MSC_RFCECNT_REG_OFFSET 0x0194U
- #define MSC_RFAECNT_REG_OFFSET 0x0198U
- #define MSC_RGUFCNT_REG_OFFSET 0x01C4U
-
- #define PTP_TSF_REG_OFFSET 0x0728U
- #define DMA_STAT_REG_OFFSET 0x1014U
- #define DMA_INTEN_REG_OFFSET 0x101CU
- #define DMA_TDTADDR_REG_OFFSET 0x1010U
- #define DMA_CTDADDR_REG_OFFSET 0x1048U
- #define DMA_CTBADDR_REG_OFFSET 0x1050U
- #define DMA_RDTADDR_REG_OFFSET 0x100CU
- #define DMA_CRDADDR_REG_OFFSET 0x104CU
- #define DMA_CRBADDR_REG_OFFSET 0x1054U
- typedef enum
- {
-
- ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U),
- ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U),
-
- ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U),
-
- ENET_MAC_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U),
- ENET_MAC_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U),
- ENET_MAC_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U),
- ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U),
- ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U),
-
- ENET_PTP_FLAG_TSSCO = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 0U),
- ENET_PTP_FLAG_TTM = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 1U),
-
- ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U),
- ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U),
- ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U),
-
- ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U),
- ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U),
- ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U),
-
- ENET_DMA_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U),
- ENET_DMA_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U),
- ENET_DMA_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U),
- ENET_DMA_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U),
- ENET_DMA_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U),
- ENET_DMA_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U),
- ENET_DMA_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U),
- ENET_DMA_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U),
- ENET_DMA_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U),
- ENET_DMA_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U),
- ENET_DMA_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U),
- ENET_DMA_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U),
- ENET_DMA_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U),
- ENET_DMA_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U),
- ENET_DMA_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U),
- ENET_DMA_FLAG_EB_DMA_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 23U),
- ENET_DMA_FLAG_EB_TRANSFER_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 24U),
- ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U),
- ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U),
- ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U),
- ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U),
- }enet_flag_enum;
- typedef enum
- {
-
- ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U),
- ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U),
- ENET_DMA_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U),
- ENET_DMA_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U),
- ENET_DMA_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U),
- ENET_DMA_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U),
- ENET_DMA_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U),
- ENET_DMA_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U),
- ENET_DMA_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U),
- ENET_DMA_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U),
- ENET_DMA_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U),
- ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U),
- ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U),
- ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U),
- ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U),
- }enet_flag_clear_enum;
- typedef enum
- {
-
- ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U),
- ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U),
-
- ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U),
- ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U),
- ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U),
-
- ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U),
- ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U),
- ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U),
-
- ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U),
- ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U),
- ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U),
- ENET_DMA_INT_TJTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 3U),
- ENET_DMA_INT_ROIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 4U),
- ENET_DMA_INT_TUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 5U),
- ENET_DMA_INT_RIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 6U),
- ENET_DMA_INT_RBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 7U),
- ENET_DMA_INT_RPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 8U),
- ENET_DMA_INT_RWTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 9U),
- ENET_DMA_INT_ETIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 10U),
- ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U),
- ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U),
- ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U),
- ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U),
- }enet_int_enum;
-
- typedef enum
- {
-
- ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U),
- ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U),
- ENET_MAC_INT_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U),
- ENET_MAC_INT_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U),
- ENET_MAC_INT_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U),
-
- ENET_MSC_INT_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U),
- ENET_MSC_INT_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U),
- ENET_MSC_INT_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U),
-
- ENET_MSC_INT_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U),
- ENET_MSC_INT_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U),
- ENET_MSC_INT_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U),
-
- ENET_DMA_INT_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U),
- ENET_DMA_INT_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U),
- ENET_DMA_INT_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U),
- ENET_DMA_INT_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U),
- ENET_DMA_INT_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U),
- ENET_DMA_INT_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U),
- ENET_DMA_INT_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U),
- ENET_DMA_INT_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U),
- ENET_DMA_INT_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U),
- ENET_DMA_INT_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U),
- ENET_DMA_INT_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U),
- ENET_DMA_INT_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U),
- ENET_DMA_INT_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U),
- ENET_DMA_INT_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U),
- ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U),
- ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U),
- ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U),
- ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U),
- }enet_int_flag_enum;
- typedef enum
- {
-
- ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U),
- ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U),
- ENET_DMA_INT_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U),
- ENET_DMA_INT_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U),
- ENET_DMA_INT_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U),
- ENET_DMA_INT_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U),
- ENET_DMA_INT_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U),
- ENET_DMA_INT_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U),
- ENET_DMA_INT_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U),
- ENET_DMA_INT_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U),
- ENET_DMA_INT_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U),
- ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U),
- ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U),
- ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U),
- ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U),
- }enet_int_flag_clear_enum;
- typedef enum
- {
- ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET,
- ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET,
- ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET,
- ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET,
- ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET,
- ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET
- }enet_desc_reg_enum;
- typedef enum
- {
- ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET,
- ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET,
- ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET,
- ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET,
- ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET,
- ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET
- }enet_msc_counter_enum;
- typedef enum
- {
- FORWARD_OPTION = BIT(0),
- DMABUS_OPTION = BIT(1),
- DMA_MAXBURST_OPTION = BIT(2),
- DMA_ARBITRATION_OPTION = BIT(3),
- STORE_OPTION = BIT(4),
- DMA_OPTION = BIT(5),
- VLAN_OPTION = BIT(6),
- FLOWCTL_OPTION = BIT(7),
- HASHH_OPTION = BIT(8),
- HASHL_OPTION = BIT(9),
- FILTER_OPTION = BIT(10),
- HALFDUPLEX_OPTION = BIT(11),
- TIMER_OPTION = BIT(12),
- INTERFRAMEGAP_OPTION = BIT(13),
- }enet_option_enum;
- typedef enum
- {
- ENET_AUTO_NEGOTIATION = 0x01u,
- ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM),
- ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD ,
- ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM,
- ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U,
- ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM)
- }enet_mediamode_enum;
- typedef enum
- {
- ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U,
- ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO,
- ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO|ENET_DMA_CTL_DTCERFD)
- }enet_chksumconf_enum;
- typedef enum
- {
- ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM,
- ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR,
- ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U,
- ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD
- }enet_frmrecept_enum;
- typedef enum
- {
- ALL_MAC_REG = 0,
- ALL_MSC_REG = 22,
- ALL_PTP_REG = 33,
- ALL_DMA_REG = 44,
- }enet_registers_type_enum;
- typedef enum
- {
- ENET_DMA_TX = ENET_DMA_STAT_TP,
- ENET_DMA_RX = ENET_DMA_STAT_RP
- }enet_dmadirection_enum;
- typedef enum
- {
- ENET_PHY_READ = (uint32_t)0x00000000,
- ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW
- }enet_phydirection_enum;
- typedef enum
- {
- ENET_REG_READ,
- ENET_REG_WRITE
- }enet_regdirection_enum;
-
- typedef enum
- {
- ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000),
- ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008),
- ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010),
- ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018)
- }enet_macaddress_enum;
- typedef enum
- {
- TXDESC_COLLISION_COUNT,
- TXDESC_BUFFER_1_ADDR,
- RXDESC_FRAME_LENGTH,
- RXDESC_BUFFER_1_SIZE,
- RXDESC_BUFFER_2_SIZE,
- RXDESC_BUFFER_1_ADDR
- }enet_descstate_enum;
- typedef enum
- {
- ENET_MSC_PRESET_NONE = 0U,
- ENET_MSC_PRESET_HALF = ENET_MSC_CTL_PMC,
- ENET_MSC_PRESET_FULL = ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM
- }enet_msc_preset_enum;
- typedef struct
- {
- uint32_t option_enable;
- uint32_t forward_frame;
- uint32_t dmabus_mode;
- uint32_t dma_maxburst;
- uint32_t dma_arbitration;
- uint32_t store_forward_mode;
- uint32_t dma_function;
- uint32_t vlan_config;
- uint32_t flow_control;
- uint32_t hashtable_high;
- uint32_t hashtable_low;
- uint32_t framesfilter_mode;
- uint32_t halfduplex_param;
- uint32_t timer_config;
- uint32_t interframegap;
- }enet_initpara_struct;
-
- typedef struct
- {
- uint32_t status;
- uint32_t control_buffer_size;
- uint32_t buffer1_addr;
- uint32_t buffer2_next_desc_addr;
- #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE
- uint32_t extended_status;
- uint32_t reserved;
- uint32_t timestamp_low;
- uint32_t timestamp_high;
- #endif
-
- } enet_descriptors_struct;
-
- typedef struct
- {
- uint32_t second;
- uint32_t nanosecond;
- uint32_t sign;
- }enet_ptp_systime_struct;
- #define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5))
- #define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0)
- #define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1)
- #define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2)
- #define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3)
- #define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
- #define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0)
- #define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1)
- #define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2)
- #define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3)
- #define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4)
- #define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5)
- #define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6)
- #define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7)
- #define ENET_TYPEFRAME_CRC_DROP_ENABLE ENET_MAC_CFG_TFCD
- #define ENET_TYPEFRAME_CRC_DROP_DISABLE ((uint32_t)0x00000000U)
- #define ENET_TYPEFRAME_CRC_DROP ENET_MAC_CFG_TFCD
- #define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U)
- #define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD
-
- #define ENET_JABBER_ENABLE ((uint32_t)0x00000000U)
- #define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD
- #define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U)
- #define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD
-
- #define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U)
- #define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD
- #define ENET_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U)
- #define ENET_RECEIVEOWN_DISABLE ENET_MAC_CFG_ROD
- #define ENET_LOOPBACKMODE_ENABLE ENET_MAC_CFG_LBM
- #define ENET_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U)
- #define ENET_MODE_FULLDUPLEX ENET_MAC_CFG_DPM
- #define ENET_MODE_HALFDUPLEX ((uint32_t)0x00000000U)
- #define ENET_CHECKSUMOFFLOAD_ENABLE ENET_MAC_CFG_IPFCO
- #define ENET_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000U)
- #define ENET_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U)
- #define ENET_RETRYTRANSMISSION_DISABLE ENET_MAC_CFG_RTD
- #define ENET_AUTO_PADCRC_DROP_ENABLE ENET_MAC_CFG_APCD
- #define ENET_AUTO_PADCRC_DROP_DISABLE ((uint32_t)0x00000000U)
- #define ENET_AUTO_PADCRC_DROP ENET_MAC_CFG_APCD
- #define ENET_DEFERRALCHECK_ENABLE ENET_MAC_CFG_DFC
- #define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U)
- #define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
- #define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0)
- #define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1)
- #define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2)
- #define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3)
-
- #define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR
- #define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U)
-
- #define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT
- #define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT)
- #define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U)
- #define ENET_SRC_FILTER ENET_MAC_FRMF_SAFLT
- #define ENET_SRC_FILTER_INVERSE ENET_MAC_FRMF_SAIFLT
- #define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U)
- #define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD
-
- #define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT
- #define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U)
- #define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT
- #define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM
- #define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U)
-
- #define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT)
- #define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF
- #define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U)
- #define ENET_MULTICAST_FILTER_NONE ENET_MAC_FRMF_MFD
- #define ENET_MULTICAST_FILTER_PASS ENET_MAC_FRMF_MFD
- #define ENET_MULTICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HMF
- #define ENET_FILTER_MODE_EITHER ENET_MAC_FRMF_HPFLT
- #define ENET_UNICAST_FILTER_EITHER (ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_HPFLT)
- #define ENET_UNICAST_FILTER_HASH ENET_MAC_FRMF_HUF
- #define ENET_UNICAST_FILTER_PERFECT ((uint32_t)0x00000000U)
- #define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF
- #define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2))
- #define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0)
- #define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1)
- #define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2)
- #define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3)
- #define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6))
- #define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11))
- #define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
- #define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
- #define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0)
- #define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1)
- #define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2)
- #define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3)
- #define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U)
- #define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP
- #define ENET_ZERO_QUANTA_PAUSE ENET_MAC_FCTL_DZQP
- #define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT
- #define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U)
-
- #define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN
- #define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U)
- #define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN
- #define ENET_TX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_TFCEN
- #define ENET_TX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U)
- #define ENET_TX_FLOWCONTROL ENET_MAC_FCTL_TFCEN
- #define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA
- #define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U)
- #define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA
-
- #define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16))
- #define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
-
- #define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC
- #define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)
-
- #define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR
- #define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR
- #define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR
- #define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD
- #define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN
- #define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN
- #define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU
- #define ENET_MAC_RECEIVER_NOT_IDLE ENET_MAC_DBG_MRNI
- #define ENET_RX_ASYNCHRONOUS_FIFO_STATE ENET_MAC_DBG_RXAFS
- #define ENET_RXFIFO_WRITING ENET_MAC_DBG_RXFW
- #define ENET_RXFIFO_READ_STATUS ENET_MAC_DBG_RXFRS
- #define ENET_RXFIFO_STATE ENET_MAC_DBG_RXFS
- #define ENET_MAC_TRANSMITTER_NOT_IDLE ENET_MAC_DBG_MTNI
- #define ENET_MAC_TRANSMITTER_STATUS ENET_MAC_DBG_SOMT
- #define ENET_PAUSE_CONDITION_STATUS ENET_MAC_DBG_PCS
- #define ENET_TXFIFO_READ_STATUS ENET_MAC_DBG_TXFRS
- #define ENET_TXFIFO_WRITING ENET_MAC_DBG_TXFW
- #define ENET_TXFIFO_NOT_EMPTY ENET_MAC_DBG_TXFNE
- #define ENET_TXFIFO_FULL ENET_MAC_DBG_TXFF
- #define GET_MAC_DBG_RXAFS(regval) GET_BITS((regval),1,2)
- #define GET_MAC_DBG_RXFRS(regval) GET_BITS((regval),5,6)
- #define GET_MAC_DBG_RXFS(regval) GET_BITS((regval),8,9)
- #define GET_MAC_DBG_SOMT(regval) GET_BITS((regval),17,18)
- #define GET_MAC_DBG_TXFRS(regval) GET_BITS((regval),20,21)
- #define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
- #define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
- #define ENET_ADDRESS_MASK_BYTE0 BIT(24)
- #define ENET_ADDRESS_MASK_BYTE1 BIT(25)
- #define ENET_ADDRESS_MASK_BYTE2 BIT(26)
- #define ENET_ADDRESS_MASK_BYTE3 BIT(27)
- #define ENET_ADDRESS_MASK_BYTE4 BIT(28)
- #define ENET_ADDRESS_MASK_BYTE5 BIT(29)
- #define ENET_ADDRESS_FILTER_SA BIT(30)
- #define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000)
-
- #define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0)) << 8)
- #define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0)
- #define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1)
- #define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2)
- #define ENET_ACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFA(3)
- #define ENET_ACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFA(4)
- #define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5)
- #define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6)
- #define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4)) << 8)
- #define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0)
- #define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1)
- #define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2)
- #define ENET_DEACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFD(3)
- #define ENET_DEACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFD(4)
- #define ENET_DEACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFD(5)
- #define ENET_DEACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFD(6)
- #define ENET_MSC_COUNTER_STOP_ROLLOVER ENET_MSC_CTL_CTSR
- #define ENET_MSC_RESET_ON_READ ENET_MSC_CTL_RTOR
- #define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ
- #define PTP_TSCTL_CKNT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16))
- #define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN
- #define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN
- #define ENET_ALL_RX_TIMESTAMP ENET_PTP_TSCTL_ARFSEN
- #define ENET_NONTYPE_FRAME_SNAPSHOT ENET_PTP_TSCTL_ESEN
- #define ENET_IPV6_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP6SEN
- #define ENET_IPV4_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP4SEN
- #define ENET_PTP_FRAME_USE_MACADDRESS_FILTER ENET_PTP_TSCTL_MAFEN
- #define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
- #define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30)
-
- #define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000)
- #define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS
- #define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U))
- #define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0))
- #define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000)
- #define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS
- #define PTP_PPSCTL_PPSOFC(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
- #define ENET_PPSOFC_1HZ PTP_PPSCTL_PPSOFC(0)
- #define ENET_PPSOFC_2HZ PTP_PPSCTL_PPSOFC(1)
- #define ENET_PPSOFC_4HZ PTP_PPSCTL_PPSOFC(2)
- #define ENET_PPSOFC_8HZ PTP_PPSCTL_PPSOFC(3)
- #define ENET_PPSOFC_16HZ PTP_PPSCTL_PPSOFC(4)
- #define ENET_PPSOFC_32HZ PTP_PPSCTL_PPSOFC(5)
- #define ENET_PPSOFC_64HZ PTP_PPSCTL_PPSOFC(6)
- #define ENET_PPSOFC_128HZ PTP_PPSCTL_PPSOFC(7)
- #define ENET_PPSOFC_256HZ PTP_PPSCTL_PPSOFC(8)
- #define ENET_PPSOFC_512HZ PTP_PPSCTL_PPSOFC(9)
- #define ENET_PPSOFC_1024HZ PTP_PPSCTL_PPSOFC(10)
- #define ENET_PPSOFC_2048HZ PTP_PPSCTL_PPSOFC(11)
- #define ENET_PPSOFC_4096HZ PTP_PPSCTL_PPSOFC(12)
- #define ENET_PPSOFC_8192HZ PTP_PPSCTL_PPSOFC(13)
- #define ENET_PPSOFC_16384HZ PTP_PPSCTL_PPSOFC(14)
- #define ENET_PPSOFC_32768HZ PTP_PPSCTL_PPSOFC(15)
- #define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2))
- #define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6)
- #define ENET_ENHANCED_DESCRIPTOR ENET_DMA_BCTL_DFM
- #define ENET_NORMAL_DESCRIPTOR ((uint32_t)0x00000000)
- #define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8))
- #define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1)
- #define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2)
- #define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4)
- #define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8)
- #define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16)
- #define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32)
- #define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL)
- #define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL)
- #define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL)
- #define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL)
- #define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL)
- #define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL)
- #define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14))
- #define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0)
- #define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1)
- #define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2)
- #define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3)
- #define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB
- #define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB
- #define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000)
- #define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17))
- #define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1)
- #define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2)
- #define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4)
- #define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8)
- #define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16)
- #define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32)
- #define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL)
- #define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL)
- #define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL)
- #define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL)
- #define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL)
- #define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL)
- #define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP
- #define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000)
- #define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA
- #define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000)
- #define ENET_MIXED_BURST_ENABLE ENET_DMA_BCTL_MB
- #define ENET_MIXED_BURST_DISABLE ((uint32_t)0x00000000)
- #define GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval),17,19)
- #define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000)
- #define ENET_RX_STATE_FETCHING BIT(17)
- #define ENET_RX_STATE_WAITING (BIT(17)|BIT(18))
- #define ENET_RX_STATE_SUSPENDED BIT(19)
- #define ENET_RX_STATE_CLOSING (BIT(17)|BIT(19))
- #define ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP
- #define GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval),20,22)
- #define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000)
- #define ENET_TX_STATE_FETCHING BIT(20)
- #define ENET_TX_STATE_WAITING BIT(21)
- #define ENET_TX_STATE_READING (BIT(20)|BIT(21))
- #define ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22))
- #define ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP
- #define GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval),23,25)
- #define ENET_ERROR_TXDATA_TRANSFER BIT(23)
- #define ENET_ERROR_READ_TRANSFER BIT(24)
- #define ENET_ERROR_DESC_ACCESS BIT(25)
- #define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3))
- #define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0)
- #define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1)
- #define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2)
- #define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3)
- #define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14))
- #define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0)
- #define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1)
- #define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2)
- #define ENET_TX_THRESHOLD_256BYTES DMA_CTL_TTHC(3)
- #define ENET_TX_THRESHOLD_40BYTES DMA_CTL_TTHC(4)
- #define ENET_TX_THRESHOLD_32BYTES DMA_CTL_TTHC(5)
- #define ENET_TX_THRESHOLD_24BYTES DMA_CTL_TTHC(6)
- #define ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7)
- #define ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD
- #define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000)
- #define ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD
- #define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000)
- #define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000)
- #define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF
- #define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF
- #define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD
- #define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000)
- #define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF << 2)
- #define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000)
- #define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF << 2)
- #define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF << 2)
- #define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000)
- #define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF << 2)
- #define ENET_SECONDFRAME_OPT_ENABLE ENET_DMA_CTL_OSF
- #define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000)
- #define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF
- #define GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval),0,15)
- #define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27)
- #define DMA_RSWDC_WDCFRS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
- #define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3))
- #define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6)
- #define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22))
- #define ENET_CHECKSUM_DISABLE TDES0_CM(0)
- #define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1)
- #define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2)
- #define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3)
- #define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0))
- #define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16))
- #define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16))
- #define GET_RDES0_FRML(regval) GET_BITS((regval),16,29)
- #define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U)
- #define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC
- #define GET_RDES1_RB1S(regval) GET_BITS((regval),0,12)
- #define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28)
- #define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
- #define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2)
- #define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
- #define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11)
- #define MAC_CFG_MASK ((uint32_t)0xFD30810FU)
- #define MAC_FCTL_MASK ((uint32_t)0x0000FF41U)
- #define DMA_CTL_MASK ((uint32_t)0xF8DE3F23U)
- #define DMA_BCTL_MASK ((uint32_t)0xF800007DU)
- #define ENET_MSC_PRESET_MASK (~(ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM))
- #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE
- #define ETH_DMATXDESC_SIZE 0x20U
- #define ETH_DMARXDESC_SIZE 0x20U
- #else
- #define ETH_DMATXDESC_SIZE 0x10U
- #define ETH_DMARXDESC_SIZE 0x10U
- #endif
- typedef enum{
- ENET_CKNT_ORDINARY = PTP_TSCTL_CKNT(0),
- ENET_CKNT_BOUNDARY = PTP_TSCTL_CKNT(1),
- ENET_CKNT_END_TO_END = PTP_TSCTL_CKNT(2),
- ENET_CKNT_PEER_TO_PEER = PTP_TSCTL_CKNT(3),
- ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI,
- ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU,
- ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU,
- ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)),
- ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU,
- ENET_SUBSECOND_DIGITAL_ROLLOVER = (int32_t)(ENET_PTP_TSCTL_SCROM | BIT(31)),
- ENET_SUBSECOND_BINARY_ROLLOVER = ENET_PTP_TSCTL_SCROM,
- ENET_SNOOPING_PTP_VERSION_2 = (int32_t)(ENET_PTP_TSCTL_PFSV| BIT(31)),
- ENET_SNOOPING_PTP_VERSION_1 = ENET_PTP_TSCTL_PFSV,
- ENET_EVENT_TYPE_MESSAGES_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_ETMSEN| BIT(31)),
- ENET_ALL_TYPE_MESSAGES_SNAPSHOT = ENET_PTP_TSCTL_ETMSEN,
- ENET_MASTER_NODE_MESSAGE_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_MNMSEN| BIT(31)),
- ENET_SLAVE_NODE_MESSAGE_SNAPSHOT = ENET_PTP_TSCTL_MNMSEN,
- }enet_ptp_function_enum;
- #define ETH_WAKEUP_REGISTER_LENGTH 8U
-
- #define ENET_MAX_FRAME_SIZE 1524U
- #define ENET_DELAY_TO ((uint32_t)0x0004FFFFU)
- #define ENET_RESET_TO ((uint32_t)0x000004FFU)
- void enet_deinit(void);
- void enet_initpara_config(enet_option_enum option, uint32_t para);
- ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept);
- ErrStatus enet_software_reset(void);
- uint32_t enet_rxframe_size_get(void);
- void enet_descriptors_chain_init(enet_dmadirection_enum direction);
- void enet_descriptors_ring_init(enet_dmadirection_enum direction);
- ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize);
- #define ENET_NOCOPY_FRAME_RECEIVE() enet_frame_receive(NULL, 0U)
- ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length);
- #define ENET_NOCOPY_FRAME_TRANSMIT(len) enet_frame_transmit(NULL, (len))
- ErrStatus enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum);
- void enet_enable(void);
- void enet_disable(void);
- void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]);
-
- ErrStatus enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[], uint8_t bufsize);
- FlagStatus enet_flag_get(enet_flag_enum enet_flag);
- void enet_flag_clear(enet_flag_clear_enum enet_flag);
- void enet_interrupt_enable(enet_int_enum enet_int);
- void enet_interrupt_disable(enet_int_enum enet_int);
- FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag);
- void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear);
- void enet_tx_enable(void);
- void enet_tx_disable(void);
- void enet_rx_enable(void);
- void enet_rx_disable(void);
- void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num);
- uint32_t enet_debug_status_get(uint32_t mac_debug);
- void enet_address_filter_enable(enet_macaddress_enum mac_addr);
- void enet_address_filter_disable(enet_macaddress_enum mac_addr);
- void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type);
- ErrStatus enet_phy_config(void);
- ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue);
- ErrStatus enet_phyloopback_enable(void);
- ErrStatus enet_phyloopback_disable(void);
- void enet_forward_feature_enable(uint32_t feature);
- void enet_forward_feature_disable(uint32_t feature);
- void enet_fliter_feature_enable(uint32_t feature);
- void enet_fliter_feature_disable(uint32_t feature);
- ErrStatus enet_pauseframe_generate(void);
- void enet_pauseframe_detect_config(uint32_t detect);
- void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold);
- void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active);
- void enet_flowcontrol_feature_enable(uint32_t feature);
- void enet_flowcontrol_feature_disable(uint32_t feature);
- uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction);
- void enet_dmaprocess_resume(enet_dmadirection_enum direction);
- void enet_rxprocess_check_recovery(void);
- ErrStatus enet_txfifo_flush(void);
- uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get);
- uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get);
- void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop);
- FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag);
- void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag);
- void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag);
- void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc);
- void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time);
- void enet_rxframe_drop(void);
- void enet_dma_feature_enable(uint32_t feature);
- void enet_dma_feature_disable(uint32_t feature);
- #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE
- uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status);
- void enet_desc_select_enhanced_mode(void);
- void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction);
- void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction);
- ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]);
- #define ENET_NOCOPY_PTPFRAME_RECEIVE_ENHANCED_MODE(ptr) enet_ptpframe_receive_enhanced_mode(NULL, 0U, (ptr))
- ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]);
- #define ENET_NOCOPY_PTPFRAME_TRANSMIT_ENHANCED_MODE(len, ptr) enet_ptpframe_transmit_enhanced_mode(NULL, (len), (ptr))
- #else
- void enet_desc_select_normal_mode(void);
- void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab);
- void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab);
- ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]);
- #define ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE(ptr) enet_ptpframe_receive_normal_mode(NULL, 0U, (ptr))
- ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]);
- #define ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE(len, ptr) enet_ptpframe_transmit_normal_mode(NULL, (len), (ptr))
- #endif
- void enet_wum_filter_register_pointer_reset(void);
- void enet_wum_filter_config(uint32_t pdata[]);
- void enet_wum_feature_enable(uint32_t feature);
- void enet_wum_feature_disable(uint32_t feature);
- void enet_msc_counters_reset(void);
-
- void enet_msc_feature_enable(uint32_t feature);
-
- void enet_msc_feature_disable(uint32_t feature);
- void enet_msc_counters_preset_config(enet_msc_preset_enum mode);
-
- uint32_t enet_msc_counters_get(enet_msc_counter_enum counter);
- uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond);
- uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond);
- void enet_ptp_feature_enable(uint32_t feature);
- void enet_ptp_feature_disable(uint32_t feature);
- ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func);
- void enet_ptp_subsecond_increment_config(uint32_t subsecond);
- void enet_ptp_timestamp_addend_config(uint32_t add);
- void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond);
- void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond);
- void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct);
- void enet_ptp_pps_output_frequency_config(uint32_t freq);
- void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg);
- void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg);
- void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct);
- void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct);
- FlagStatus enet_ptp_flag_get(uint32_t flag);
- void enet_initpara_reset(void);
- #ifdef USE_DELAY
- #define _ENET_DELAY_ delay_ms
- #else
- #define _ENET_DELAY_ enet_delay
- #endif
- #endif
|