123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873 |
- #include "gd32f30x_spi.h"
- #define SPI_ERROR_HANDLE(s) do{}while(1)
- #define SPI_INIT_MASK ((uint32_t)0x00003040U)
- #define I2S_INIT_MASK ((uint32_t)0x0000F047U)
- #define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U)
- #define I2S1_CLOCK_SEL ((uint32_t)0x00020000U)
- #define I2S2_CLOCK_SEL ((uint32_t)0x00040000U)
- #define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U)
- #define I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U)
- void spi_i2s_deinit(uint32_t spi_periph)
- {
- switch(spi_periph){
- case SPI0:
-
- rcu_periph_reset_enable(RCU_SPI0RST);
- rcu_periph_reset_disable(RCU_SPI0RST);
- break;
- case SPI1:
-
- rcu_periph_reset_enable(RCU_SPI1RST);
- rcu_periph_reset_disable(RCU_SPI1RST);
- break;
- case SPI2:
-
- rcu_periph_reset_enable(RCU_SPI2RST);
- rcu_periph_reset_disable(RCU_SPI2RST);
- break;
- default :
- break;
- }
- }
- void spi_struct_para_init(spi_parameter_struct *spi_struct)
- {
-
- spi_struct->device_mode = SPI_SLAVE;
- spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX;
- spi_struct->frame_size = SPI_FRAMESIZE_8BIT;
- spi_struct->nss = SPI_NSS_HARD;
- spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;
- spi_struct->prescale = SPI_PSC_2;
- spi_struct->endian = SPI_ENDIAN_MSB;
- }
- void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct)
- {
- uint32_t reg = 0U;
- reg = SPI_CTL0(spi_periph);
- reg &= SPI_INIT_MASK;
-
- reg |= spi_struct->device_mode;
-
- reg |= spi_struct->trans_mode;
-
- reg |= spi_struct->frame_size;
-
- reg |= spi_struct->nss;
-
- reg |= spi_struct->endian;
-
- reg |= spi_struct->clock_polarity_phase;
-
- reg |= spi_struct->prescale;
-
- SPI_CTL0(spi_periph) = (uint32_t)reg;
- SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL);
- }
- void spi_enable(uint32_t spi_periph)
- {
- SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN;
- }
- void spi_disable(uint32_t spi_periph)
- {
- SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN);
- }
- void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl)
- {
- uint32_t reg= 0U;
- reg = SPI_I2SCTL(spi_periph);
- reg &= I2S_INIT_MASK;
-
- reg |= (uint32_t)SPI_I2SCTL_I2SSEL;
-
- reg |= (uint32_t)i2s_mode;
-
- reg |= (uint32_t)i2s_standard;
-
- reg |= (uint32_t)i2s_ckpl;
-
- SPI_I2SCTL(spi_periph) = (uint32_t)reg;
- }
- void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout)
- {
- uint32_t i2sdiv = 2U, i2sof = 0U;
- uint32_t clks = 0U;
- uint32_t i2sclock = 0U;
-
- #ifdef GD32F30X_CL
- uint32_t pll2mf_4 = 0U;
- #endif
-
-
- if(0U == i2s_audiosample){
- SPI_ERROR_HANDLE("the parameter can not be 0 \r\n");
- }
-
- SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE;
- #ifdef GD32F30X_CL
-
- if(((uint32_t)spi_periph) == SPI1){
-
- clks = I2S1_CLOCK_SEL;
- }else{
-
- clks = I2S2_CLOCK_SEL;
- }
-
- if(0U != (RCU_CFG1 & clks)){
-
- clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> 12U);
-
- pll2mf_4 = RCU_CFG1 & RCU_CFG1_PLL2MF_4;
-
- if( 0U == pll2mf_4){
- if((clks > 5U) && (clks < 15U)){
-
- clks += 2U;
- }else{
- if(15U == clks){
-
- clks = 20U;
- }
- }
- }else{
- if(clks < 15U){
-
- clks += 18U;
- }else{
- if(15U == clks){
-
- clks = 40U;
- }
- }
- }
-
- i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> 4U) + 1U);
-
- i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U);
- }else{
-
- i2sclock = rcu_clock_freq_get(CK_SYS);
- }
- #else
-
- i2sclock = rcu_clock_freq_get(CK_SYS);
- #endif
-
-
- if(I2S_MCKOUT_ENABLE == i2s_mckout){
- clks = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample);
- }else{
- if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat){
- clks = (uint32_t)(((i2sclock / 32U) *10U ) / i2s_audiosample);
- }else{
- clks = (uint32_t)(((i2sclock / 64U) *10U ) / i2s_audiosample);
- }
- }
-
-
- clks = (clks + 5U) / 10U;
- i2sof = (clks & 0x00000001U);
- i2sdiv = ((clks - i2sof) / 2U);
- i2sof = (i2sof << 8U);
-
- if((i2sdiv < 2U) || (i2sdiv > 255U)){
- i2sdiv = 2U;
- i2sof = 0U;
- }
-
- SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | i2s_mckout);
-
- SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN));
-
- SPI_I2SCTL(spi_periph) |= (uint32_t)i2s_frameformat;
- }
- void i2s_enable(uint32_t spi_periph)
- {
- SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN;
- }
- void i2s_disable(uint32_t spi_periph)
- {
- SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN);
- }
- void spi_nss_output_enable(uint32_t spi_periph)
- {
- SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV;
- }
- void spi_nss_output_disable(uint32_t spi_periph)
- {
- SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV);
- }
- void spi_nss_internal_high(uint32_t spi_periph)
- {
- SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS;
- }
- void spi_nss_internal_low(uint32_t spi_periph)
- {
- SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS);
- }
- void spi_dma_enable(uint32_t spi_periph, uint8_t dma)
- {
- if(SPI_DMA_TRANSMIT == dma){
- SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN;
- }else{
- SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN;
- }
- }
- void spi_dma_disable(uint32_t spi_periph, uint8_t dma)
- {
- if(SPI_DMA_TRANSMIT == dma){
- SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN);
- }else{
- SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN);
- }
- }
- void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format)
- {
-
- SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16);
-
- SPI_CTL0(spi_periph) |= (uint32_t)frame_format;
- }
- void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data)
- {
- SPI_DATA(spi_periph) = (uint32_t)data;
- }
- uint16_t spi_i2s_data_receive(uint32_t spi_periph)
- {
- return ((uint16_t)SPI_DATA(spi_periph));
- }
- void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction)
- {
- if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){
-
- SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT;
- }else{
-
- SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE;
- }
- }
- void spi_i2s_format_error_clear(uint32_t spi_periph, uint32_t flag)
- {
- SPI_STAT(spi_periph) = (uint32_t)(~flag);
- }
- void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly)
- {
-
- SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly;
- }
- uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
- {
- return ((uint16_t)SPI_CRCPOLY(spi_periph));
- }
- void spi_crc_on(uint32_t spi_periph)
- {
- SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
- }
- void spi_crc_off(uint32_t spi_periph)
- {
- SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN);
- }
- void spi_crc_next(uint32_t spi_periph)
- {
- SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT;
- }
- uint16_t spi_crc_get(uint32_t spi_periph,uint8_t crc)
- {
- if(SPI_CRC_TX == crc){
- return ((uint16_t)(SPI_TCRC(spi_periph)));
- }else{
- return ((uint16_t)(SPI_RCRC(spi_periph)));
- }
- }
- void spi_crc_error_clear(uint32_t spi_periph)
- {
- SPI_STAT(spi_periph) = (uint32_t)(~SPI_FLAG_CRCERR);
- }
- void spi_ti_mode_enable(uint32_t spi_periph)
- {
- SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD;
- }
- void spi_ti_mode_disable(uint32_t spi_periph)
- {
- SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD);
- }
- void spi_nssp_mode_enable(uint32_t spi_periph)
- {
- SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP;
- }
- void spi_nssp_mode_disable(uint32_t spi_periph)
- {
- SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP);
- }
- void spi_quad_enable(uint32_t spi_periph)
- {
- SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD;
- }
- void spi_quad_disable(uint32_t spi_periph)
- {
- SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD);
- }
- void spi_quad_write_enable(uint32_t spi_periph)
- {
- SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD);
- }
- void spi_quad_read_enable(uint32_t spi_periph)
- {
- SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD;
- }
- void spi_quad_io23_output_enable(uint32_t spi_periph)
- {
- SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV;
- }
-
- void spi_quad_io23_output_disable(uint32_t spi_periph)
- {
- SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV);
- }
- void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
- {
- switch(interrupt){
-
- case SPI_I2S_INT_TBE:
- SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE;
- break;
-
- case SPI_I2S_INT_RBNE:
- SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE;
- break;
-
- case SPI_I2S_INT_ERR:
- SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE;
- break;
- default:
- break;
- }
- }
- void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
- {
- switch(interrupt){
-
- case SPI_I2S_INT_TBE:
- SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
- break;
-
- case SPI_I2S_INT_RBNE:
- SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE);
- break;
-
- case SPI_I2S_INT_ERR:
- SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE);
- break;
- default :
- break;
- }
- }
- FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
- {
- uint32_t reg1 = SPI_STAT(spi_periph);
- uint32_t reg2 = SPI_CTL1(spi_periph);
- switch(interrupt){
-
- case SPI_I2S_INT_FLAG_TBE:
- reg1 = reg1 & SPI_STAT_TBE;
- reg2 = reg2 & SPI_CTL1_TBEIE;
- break;
-
- case SPI_I2S_INT_FLAG_RBNE:
- reg1 = reg1 & SPI_STAT_RBNE;
- reg2 = reg2 & SPI_CTL1_RBNEIE;
- break;
-
- case SPI_I2S_INT_FLAG_RXORERR:
- reg1 = reg1 & SPI_STAT_RXORERR;
- reg2 = reg2 & SPI_CTL1_ERRIE;
- break;
-
- case SPI_INT_FLAG_CONFERR:
- reg1 = reg1 & SPI_STAT_CONFERR;
- reg2 = reg2 & SPI_CTL1_ERRIE;
- break;
-
- case SPI_INT_FLAG_CRCERR:
- reg1 = reg1 & SPI_STAT_CRCERR;
- reg2 = reg2 & SPI_CTL1_ERRIE;
- break;
-
- case I2S_INT_FLAG_TXURERR:
- reg1 = reg1 & SPI_STAT_TXURERR;
- reg2 = reg2 & SPI_CTL1_ERRIE;
- break;
-
- case SPI_I2S_INT_FLAG_FERR:
- reg1 = reg1 & SPI_STAT_FERR;
- reg2 = reg2 & SPI_CTL1_ERRIE;
- break;
- default :
- break;
- }
-
- if(reg1 && reg2){
- return SET;
- }else{
- return RESET;
- }
- }
- FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
- {
- if(SPI_STAT(spi_periph) & flag){
- return SET;
- }else{
- return RESET;
- }
- }
|