stm32f2xx_rcc.c 71 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f2xx_rcc.c
  4. * @author MCD Application Team
  5. * @version V1.1.3
  6. * @date 31-December-2021
  7. * @brief This file provides firmware functions to manage the following
  8. * functionalities of the Reset and clock control (RCC) peripheral:
  9. * - Internal/external clocks, PLL, CSS and MCO configuration
  10. * - System, AHB and APB busses clocks configuration
  11. * - Peripheral clocks configuration
  12. * - Interrupts and flags management
  13. *
  14. * @verbatim
  15. *
  16. * ===================================================================
  17. * RCC specific features
  18. * ===================================================================
  19. *
  20. * After reset the device is running from Internal High Speed oscillator
  21. * (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
  22. * and I-Cache are disabled, and all peripherals are off except internal
  23. * SRAM, Flash and JTAG.
  24. * - There is no prescaler on High speed (AHB) and Low speed (APB) busses;
  25. * all peripherals mapped on these busses are running at HSI speed.
  26. * - The clock for all peripherals is switched off, except the SRAM and FLASH.
  27. * - All GPIOs are in input floating state, except the JTAG pins which
  28. * are assigned to be used for debug purpose.
  29. *
  30. * Once the device started from reset, the user application has to:
  31. * - Configure the clock source to be used to drive the System clock
  32. * (if the application needs higher frequency/performance)
  33. * - Configure the System clock frequency and Flash settings
  34. * - Configure the AHB and APB busses prescalers
  35. * - Enable the clock for the peripheral(s) to be used
  36. * - Configure the clock source(s) for peripherals which clocks are not
  37. * derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
  38. *
  39. * @endverbatim
  40. *
  41. ******************************************************************************
  42. * @attention
  43. *
  44. * Copyright (c) 2012 STMicroelectronics.
  45. * All rights reserved.
  46. *
  47. * This software is licensed under terms that can be found in the LICENSE file
  48. * in the root directory of this software component.
  49. * If no LICENSE file comes with this software, it is provided AS-IS.
  50. *
  51. ******************************************************************************
  52. */
  53. /* Includes ------------------------------------------------------------------*/
  54. #include "stm32f2xx_rcc.h"
  55. /** @addtogroup STM32F2xx_StdPeriph_Driver
  56. * @{
  57. */
  58. /** @defgroup RCC
  59. * @brief RCC driver modules
  60. * @{
  61. */
  62. /* Private typedef -----------------------------------------------------------*/
  63. /* Private define ------------------------------------------------------------*/
  64. /* ------------ RCC registers bit address in the alias region ----------- */
  65. #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
  66. /* --- CR Register ---*/
  67. /* Alias word address of HSION bit */
  68. #define CR_OFFSET (RCC_OFFSET + 0x00)
  69. #define HSION_BitNumber 0x00
  70. #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
  71. /* Alias word address of CSSON bit */
  72. #define CSSON_BitNumber 0x13
  73. #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
  74. /* Alias word address of PLLON bit */
  75. #define PLLON_BitNumber 0x18
  76. #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
  77. /* Alias word address of PLLI2SON bit */
  78. #define PLLI2SON_BitNumber 0x1A
  79. #define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
  80. /* --- CFGR Register ---*/
  81. /* Alias word address of I2SSRC bit */
  82. #define CFGR_OFFSET (RCC_OFFSET + 0x08)
  83. #define I2SSRC_BitNumber 0x17
  84. #define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
  85. /* --- BDCR Register ---*/
  86. /* Alias word address of RTCEN bit */
  87. #define BDCR_OFFSET (RCC_OFFSET + 0x70)
  88. #define RTCEN_BitNumber 0x0F
  89. #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
  90. /* Alias word address of BDRST bit */
  91. #define BDRST_BitNumber 0x10
  92. #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
  93. /* --- CSR Register ---*/
  94. /* Alias word address of LSION bit */
  95. #define CSR_OFFSET (RCC_OFFSET + 0x74)
  96. #define LSION_BitNumber 0x00
  97. #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
  98. /* ---------------------- RCC registers bit mask ------------------------ */
  99. /* CFGR register bit mask */
  100. #define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)
  101. #define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF)
  102. /* RCC Flag Mask */
  103. #define FLAG_MASK ((uint8_t)0x1F)
  104. /* CR register byte 3 (Bits[23:16]) base address */
  105. #define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
  106. /* CIR register byte 2 (Bits[15:8]) base address */
  107. #define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
  108. /* CIR register byte 3 (Bits[23:16]) base address */
  109. #define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
  110. /* BDCR register base address */
  111. #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
  112. /* Private macro -------------------------------------------------------------*/
  113. /* Private variables ---------------------------------------------------------*/
  114. static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
  115. /* Private function prototypes -----------------------------------------------*/
  116. /* Private functions ---------------------------------------------------------*/
  117. /** @defgroup RCC_Private_Functions
  118. * @{
  119. */
  120. /** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
  121. * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
  122. *
  123. @verbatim
  124. ===============================================================================
  125. Internal/external clocks, PLL, CSS and MCO configuration functions
  126. ===============================================================================
  127. This section provide functions allowing to configure the internal/external clocks,
  128. PLLs, CSS and MCO pins.
  129. 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
  130. the PLL as System clock source.
  131. 2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
  132. clock source.
  133. 3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
  134. through the PLL as System clock source. Can be used also as RTC clock source.
  135. 4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
  136. 5. PLL (clocked by HSI or HSE), featuring two different output clocks:
  137. - The first output is used to generate the high speed system clock (up to 120 MHz)
  138. - The second output is used to generate the clock for the USB OTG FS (48 MHz),
  139. the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
  140. 6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve
  141. high-quality audio performance on the I2S interface.
  142. 7. CSS (Clock security system), once enable and if a HSE clock failure occurs
  143. (HSE used directly or through PLL as System clock source), the System clock
  144. is automatically switched to HSI and an interrupt is generated if enabled.
  145. The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt)
  146. exception vector.
  147. 8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
  148. clock (through a configurable prescaler) on PA8 pin.
  149. 9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
  150. clock (through a configurable prescaler) on PC9 pin.
  151. @endverbatim
  152. * @{
  153. */
  154. /**
  155. * @brief Resets the RCC clock configuration to the default reset state.
  156. * @note The default reset state of the clock configuration is given below:
  157. * - HSI ON and used as system clock source
  158. * - HSE, PLL and PLLI2S OFF
  159. * - AHB, APB1 and APB2 prescaler set to 1.
  160. * - CSS, MCO1 and MCO2 OFF
  161. * - All interrupts disabled
  162. * @note This function doesn't modify the configuration of the
  163. * - Peripheral clocks
  164. * - LSI, LSE and RTC clocks
  165. * @param None
  166. * @retval None
  167. */
  168. void RCC_DeInit(void)
  169. {
  170. /* Set HSION bit */
  171. RCC->CR |= (uint32_t)0x00000001;
  172. /* Reset CFGR register */
  173. RCC->CFGR = 0x00000000;
  174. /* Reset HSEON, CSSON and PLLON bits */
  175. RCC->CR &= (uint32_t)0xFEF6FFFF;
  176. /* Reset PLLCFGR register */
  177. RCC->PLLCFGR = 0x24003010;
  178. /* Reset HSEBYP bit */
  179. RCC->CR &= (uint32_t)0xFFFBFFFF;
  180. /* Disable all interrupts */
  181. RCC->CIR = 0x00000000;
  182. }
  183. /**
  184. * @brief Configures the External High Speed oscillator (HSE).
  185. * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
  186. * software should wait on HSERDY flag to be set indicating that HSE clock
  187. * is stable and can be used to clock the PLL and/or system clock.
  188. * @note HSE state can not be changed if it is used directly or through the
  189. * PLL as system clock. In this case, you have to select another source
  190. * of the system clock then change the HSE state (ex. disable it).
  191. * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
  192. * @note This function reset the CSSON bit, so if the Clock security system(CSS)
  193. * was previously enabled you have to enable it again after calling this
  194. * function.
  195. * @param RCC_HSE: specifies the new state of the HSE.
  196. * This parameter can be one of the following values:
  197. * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
  198. * 6 HSE oscillator clock cycles.
  199. * @arg RCC_HSE_ON: turn ON the HSE oscillator
  200. * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
  201. * @retval None
  202. */
  203. void RCC_HSEConfig(uint8_t RCC_HSE)
  204. {
  205. /* Check the parameters */
  206. assert_param(IS_RCC_HSE(RCC_HSE));
  207. /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
  208. *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
  209. /* Set the new HSE configuration -------------------------------------------*/
  210. *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
  211. }
  212. /**
  213. * @brief Waits for HSE start-up.
  214. * @note This functions waits on HSERDY flag to be set and return SUCCESS if
  215. * this flag is set, otherwise returns ERROR if the timeout is reached
  216. * and this flag is not set. The timeout value is defined by the constant
  217. * HSE_STARTUP_TIMEOUT in stm32f2xx.h file. You can tailor it depending
  218. * on the HSE crystal used in your application.
  219. * @param None
  220. * @retval An ErrorStatus enumeration value:
  221. * - SUCCESS: HSE oscillator is stable and ready to use
  222. * - ERROR: HSE oscillator not yet ready
  223. */
  224. ErrorStatus RCC_WaitForHSEStartUp(void)
  225. {
  226. __IO uint32_t startupcounter = 0;
  227. ErrorStatus status = ERROR;
  228. FlagStatus hsestatus = RESET;
  229. /* Wait till HSE is ready and if Time out is reached exit */
  230. do
  231. {
  232. hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
  233. startupcounter++;
  234. } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
  235. if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
  236. {
  237. status = SUCCESS;
  238. }
  239. else
  240. {
  241. status = ERROR;
  242. }
  243. return (status);
  244. }
  245. /**
  246. * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
  247. * @note The calibration is used to compensate for the variations in voltage
  248. * and temperature that influence the frequency of the internal HSI RC.
  249. * @param HSICalibrationValue: specifies the calibration trimming value.
  250. * This parameter must be a number between 0 and 0x1F.
  251. * @retval None
  252. */
  253. void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
  254. {
  255. uint32_t tmpreg = 0;
  256. /* Check the parameters */
  257. assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
  258. tmpreg = RCC->CR;
  259. /* Clear HSITRIM[4:0] bits */
  260. tmpreg &= ~RCC_CR_HSITRIM;
  261. /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
  262. tmpreg |= (uint32_t)HSICalibrationValue << 3;
  263. /* Store the new value */
  264. RCC->CR = tmpreg;
  265. }
  266. /**
  267. * @brief Enables or disables the Internal High Speed oscillator (HSI).
  268. * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
  269. * It is used (enabled by hardware) as system clock source after startup
  270. * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
  271. * of the HSE used directly or indirectly as system clock (if the Clock
  272. * Security System CSS is enabled).
  273. * @note HSI can not be stopped if it is used as system clock source. In this case,
  274. * you have to select another source of the system clock then stop the HSI.
  275. * @note After enabling the HSI, the application software should wait on HSIRDY
  276. * flag to be set indicating that HSI clock is stable and can be used as
  277. * system clock source.
  278. * @param NewState: new state of the HSI.
  279. * This parameter can be: ENABLE or DISABLE.
  280. * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
  281. * clock cycles.
  282. * @retval None
  283. */
  284. void RCC_HSICmd(FunctionalState NewState)
  285. {
  286. /* Check the parameters */
  287. assert_param(IS_FUNCTIONAL_STATE(NewState));
  288. *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
  289. }
  290. /**
  291. * @brief Configures the External Low Speed oscillator (LSE).
  292. * @note As the LSE is in the Backup domain and write access is denied to
  293. * this domain after reset, you have to enable write access using
  294. * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
  295. * (to be done once after reset).
  296. * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
  297. * software should wait on LSERDY flag to be set indicating that LSE clock
  298. * is stable and can be used to clock the RTC.
  299. * @note Care must be taken when using this function to configure LSE mode
  300. * as it clears systematically the LSEON bit before any new configuration.
  301. * @param RCC_LSE: specifies the new state of the LSE.
  302. * This parameter can be one of the following values:
  303. * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
  304. * 6 LSE oscillator clock cycles.
  305. * @arg RCC_LSE_ON: turn ON the LSE oscillator
  306. * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
  307. * @retval None
  308. */
  309. void RCC_LSEConfig(uint8_t RCC_LSE)
  310. {
  311. /* Check the parameters */
  312. assert_param(IS_RCC_LSE(RCC_LSE));
  313. /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
  314. /* Reset LSEON bit */
  315. *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
  316. /* Reset LSEBYP bit */
  317. *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
  318. /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
  319. switch (RCC_LSE)
  320. {
  321. case RCC_LSE_ON:
  322. /* Set LSEON bit */
  323. *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
  324. break;
  325. case RCC_LSE_Bypass:
  326. /* Set LSEBYP and LSEON bits */
  327. *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
  328. break;
  329. default:
  330. break;
  331. }
  332. }
  333. /**
  334. * @brief Enables or disables the Internal Low Speed oscillator (LSI).
  335. * @note After enabling the LSI, the application software should wait on
  336. * LSIRDY flag to be set indicating that LSI clock is stable and can
  337. * be used to clock the IWDG and/or the RTC.
  338. * @note LSI can not be disabled if the IWDG is running.
  339. * @param NewState: new state of the LSI.
  340. * This parameter can be: ENABLE or DISABLE.
  341. * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
  342. * clock cycles.
  343. * @retval None
  344. */
  345. void RCC_LSICmd(FunctionalState NewState)
  346. {
  347. /* Check the parameters */
  348. assert_param(IS_FUNCTIONAL_STATE(NewState));
  349. *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
  350. }
  351. /**
  352. * @brief Configures the main PLL clock source, multiplication and division factors.
  353. * @note This function must be used only when the main PLL is disabled.
  354. *
  355. * @param RCC_PLLSource: specifies the PLL entry clock source.
  356. * This parameter can be one of the following values:
  357. * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
  358. * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
  359. * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
  360. *
  361. * @param PLLM: specifies the division factor for PLL VCO input clock
  362. * This parameter must be a number between 0 and 63.
  363. * @note You have to set the PLLM parameter correctly to ensure that the VCO input
  364. * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
  365. * of 2 MHz to limit PLL jitter.
  366. *
  367. * @param PLLN: specifies the multiplication factor for PLL VCO output clock
  368. * This parameter must be a number between 192 and 432.
  369. * @note You have to set the PLLN parameter correctly to ensure that the VCO
  370. * output frequency is between 192 and 432 MHz.
  371. *
  372. * @param PLLP: specifies the division factor for main system clock (SYSCLK)
  373. * This parameter must be a number in the range {2, 4, 6, or 8}.
  374. * @note You have to set the PLLP parameter correctly to not exceed 120 MHz on
  375. * the System clock frequency.
  376. *
  377. * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
  378. * This parameter must be a number between 4 and 15.
  379. * @note If the USB OTG FS is used in your application, you have to set the
  380. * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
  381. * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
  382. * correctly.
  383. *
  384. * @retval None
  385. */
  386. void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
  387. {
  388. /* Check the parameters */
  389. assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
  390. assert_param(IS_RCC_PLLM_VALUE(PLLM));
  391. assert_param(IS_RCC_PLLN_VALUE(PLLN));
  392. assert_param(IS_RCC_PLLP_VALUE(PLLP));
  393. assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
  394. RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
  395. (PLLQ << 24);
  396. }
  397. /**
  398. * @brief Enables or disables the main PLL.
  399. * @note After enabling the main PLL, the application software should wait on
  400. * PLLRDY flag to be set indicating that PLL clock is stable and can
  401. * be used as system clock source.
  402. * @note The main PLL can not be disabled if it is used as system clock source
  403. * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
  404. * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE.
  405. * @retval None
  406. */
  407. void RCC_PLLCmd(FunctionalState NewState)
  408. {
  409. /* Check the parameters */
  410. assert_param(IS_FUNCTIONAL_STATE(NewState));
  411. *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
  412. }
  413. /**
  414. * @brief Configures the PLLI2S clock multiplication and division factors.
  415. *
  416. * @note PLLI2S is available only in Silicon RevisionB and RevisionY.
  417. * @note This function must be used only when the PLLI2S is disabled.
  418. * @note PLLI2S clock source is common with the main PLL (configured in
  419. * RCC_PLLConfig function )
  420. *
  421. * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
  422. * This parameter must be a number between 192 and 432.
  423. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
  424. * output frequency is between 192 and 432 MHz.
  425. *
  426. * @param PLLI2SR: specifies the division factor for I2S clock
  427. * This parameter must be a number between 2 and 7.
  428. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
  429. * on the I2S clock frequency.
  430. *
  431. * @retval None
  432. */
  433. void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
  434. {
  435. /* Check the parameters */
  436. assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
  437. assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
  438. RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
  439. }
  440. /**
  441. * @brief Enables or disables the PLLI2S.
  442. * @note PLLI2S is available only in RevisionB and RevisionY
  443. * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
  444. * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
  445. * @retval None
  446. */
  447. void RCC_PLLI2SCmd(FunctionalState NewState)
  448. {
  449. /* Check the parameters */
  450. assert_param(IS_FUNCTIONAL_STATE(NewState));
  451. *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
  452. }
  453. /**
  454. * @brief Enables or disables the Clock Security System.
  455. * @note If a failure is detected on the HSE oscillator clock, this oscillator
  456. * is automatically disabled and an interrupt is generated to inform the
  457. * software about the failure (Clock Security System Interrupt, CSSI),
  458. * allowing the MCU to perform rescue operations. The CSSI is linked to
  459. * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
  460. * @param NewState: new state of the Clock Security System.
  461. * This parameter can be: ENABLE or DISABLE.
  462. * @retval None
  463. */
  464. void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
  465. {
  466. /* Check the parameters */
  467. assert_param(IS_FUNCTIONAL_STATE(NewState));
  468. *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
  469. }
  470. /**
  471. * @brief Selects the clock source to output on MCO1 pin(PA8).
  472. * @note PA8 should be configured in alternate function mode.
  473. * @param RCC_MCO1Source: specifies the clock source to output.
  474. * This parameter can be one of the following values:
  475. * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
  476. * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
  477. * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
  478. * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
  479. * @param RCC_MCO1Div: specifies the MCO1 prescaler.
  480. * This parameter can be one of the following values:
  481. * @arg RCC_MCO1Div_1: no division applied to MCO1 clock
  482. * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock
  483. * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock
  484. * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock
  485. * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock
  486. * @retval None
  487. */
  488. void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
  489. {
  490. uint32_t tmpreg = 0;
  491. /* Check the parameters */
  492. assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));
  493. assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));
  494. tmpreg = RCC->CFGR;
  495. /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
  496. tmpreg &= CFGR_MCO1_RESET_MASK;
  497. /* Select MCO1 clock source and prescaler */
  498. tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
  499. /* Store the new value */
  500. RCC->CFGR = tmpreg;
  501. }
  502. /**
  503. * @brief Selects the clock source to output on MCO2 pin(PC9).
  504. * @note PC9 should be configured in alternate function mode.
  505. * @param RCC_MCO2Source: specifies the clock source to output.
  506. * This parameter can be one of the following values:
  507. * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
  508. * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source
  509. * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
  510. * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
  511. * @param RCC_MCO2Div: specifies the MCO2 prescaler.
  512. * This parameter can be one of the following values:
  513. * @arg RCC_MCO2Div_1: no division applied to MCO2 clock
  514. * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock
  515. * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock
  516. * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock
  517. * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock
  518. * @retval None
  519. */
  520. void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
  521. {
  522. uint32_t tmpreg = 0;
  523. /* Check the parameters */
  524. assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));
  525. assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
  526. tmpreg = RCC->CFGR;
  527. /* Clear MCO2 and MCO2PRE[2:0] bits */
  528. tmpreg &= CFGR_MCO2_RESET_MASK;
  529. /* Select MCO2 clock source and prescaler */
  530. tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
  531. /* Store the new value */
  532. RCC->CFGR = tmpreg;
  533. }
  534. /**
  535. * @}
  536. */
  537. /** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
  538. * @brief System, AHB and APB busses clocks configuration functions
  539. *
  540. @verbatim
  541. ===============================================================================
  542. System, AHB and APB busses clocks configuration functions
  543. ===============================================================================
  544. This section provide functions allowing to configure the System, AHB, APB1 and
  545. APB2 busses clocks.
  546. 1. Several clock sources can be used to drive the System clock (SYSCLK): HSI,
  547. HSE and PLL.
  548. The AHB clock (HCLK) is derived from System clock through configurable prescaler
  549. and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...).
  550. APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through
  551. configurable prescalers and used to clock the peripherals mapped on these busses.
  552. You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
  553. @note All the peripheral clocks are derived from the System clock (SYSCLK) except:
  554. - I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
  555. from an external clock mapped on the I2S_CKIN pin.
  556. You have to use RCC_I2SCLKConfig() function to configure this clock.
  557. - RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
  558. divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
  559. functions to configure this clock.
  560. - USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
  561. to work correctly, while the SDIO require a frequency equal or lower than
  562. to 48. This clock is derived of the main PLL through PLLQ divider.
  563. - IWDG clock which is always the LSI clock.
  564. 2. The maximum frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz.
  565. Depending on the device voltage range, the maximum frequency should be
  566. adapted accordingly:
  567. +-------------------------------------------------------------------------------------+
  568. | Latency | HCLK clock frequency (MHz) |
  569. | |---------------------------------------------------------------------|
  570. | | voltage range | voltage range | voltage range | voltage range |
  571. | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
  572. |---------------|----------------|----------------|-----------------|-----------------|
  573. |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
  574. |---------------|----------------|----------------|-----------------|-----------------|
  575. |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
  576. |---------------|----------------|----------------|-----------------|-----------------|
  577. |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
  578. |---------------|----------------|----------------|-----------------|-----------------|
  579. |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
  580. |---------------|----------------|----------------|-----------------|-----------------|
  581. |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
  582. |---------------|----------------|----------------|-----------------|-----------------|
  583. |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 |
  584. |---------------|----------------|----------------|-----------------|-----------------|
  585. |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 |
  586. |---------------|----------------|----------------|-----------------|-----------------|
  587. |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120|
  588. +-------------------------------------------------------------------------------------+
  589. @endverbatim
  590. * @{
  591. */
  592. /**
  593. * @brief Configures the system clock (SYSCLK).
  594. * @note The HSI is used (enabled by hardware) as system clock source after
  595. * startup from Reset, wake-up from STOP and STANDBY mode, or in case
  596. * of failure of the HSE used directly or indirectly as system clock
  597. * (if the Clock Security System CSS is enabled).
  598. * @note A switch from one clock source to another occurs only if the target
  599. * clock source is ready (clock stable after startup delay or PLL locked).
  600. * If a clock source which is not yet ready is selected, the switch will
  601. * occur when the clock source will be ready.
  602. * You can use RCC_GetSYSCLKSource() function to know which clock is
  603. * currently used as system clock source.
  604. * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
  605. * This parameter can be one of the following values:
  606. * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
  607. * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
  608. * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
  609. * @retval None
  610. */
  611. void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
  612. {
  613. uint32_t tmpreg = 0;
  614. /* Check the parameters */
  615. assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
  616. tmpreg = RCC->CFGR;
  617. /* Clear SW[1:0] bits */
  618. tmpreg &= ~RCC_CFGR_SW;
  619. /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
  620. tmpreg |= RCC_SYSCLKSource;
  621. /* Store the new value */
  622. RCC->CFGR = tmpreg;
  623. }
  624. /**
  625. * @brief Returns the clock source used as system clock.
  626. * @param None
  627. * @retval The clock source used as system clock. The returned value can be one
  628. * of the following:
  629. * - 0x00: HSI used as system clock
  630. * - 0x04: HSE used as system clock
  631. * - 0x08: PLL used as system clock
  632. */
  633. uint8_t RCC_GetSYSCLKSource(void)
  634. {
  635. return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
  636. }
  637. /**
  638. * @brief Configures the AHB clock (HCLK).
  639. * @note Depending on the device voltage range, the software has to set correctly
  640. * these bits to ensure that HCLK not exceed the maximum allowed frequency
  641. * (for more details refer to section above
  642. * "CPU, AHB and APB busses clocks configuration functions")
  643. * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
  644. * the system clock (SYSCLK).
  645. * This parameter can be one of the following values:
  646. * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
  647. * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
  648. * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
  649. * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
  650. * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
  651. * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
  652. * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
  653. * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
  654. * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
  655. * @retval None
  656. */
  657. void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
  658. {
  659. uint32_t tmpreg = 0;
  660. /* Check the parameters */
  661. assert_param(IS_RCC_HCLK(RCC_SYSCLK));
  662. tmpreg = RCC->CFGR;
  663. /* Clear HPRE[3:0] bits */
  664. tmpreg &= ~RCC_CFGR_HPRE;
  665. /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
  666. tmpreg |= RCC_SYSCLK;
  667. /* Store the new value */
  668. RCC->CFGR = tmpreg;
  669. }
  670. /**
  671. * @brief Configures the Low Speed APB clock (PCLK1).
  672. * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
  673. * the AHB clock (HCLK).
  674. * This parameter can be one of the following values:
  675. * @arg RCC_HCLK_Div1: APB1 clock = HCLK
  676. * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
  677. * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
  678. * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
  679. * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
  680. * @retval None
  681. */
  682. void RCC_PCLK1Config(uint32_t RCC_HCLK)
  683. {
  684. uint32_t tmpreg = 0;
  685. /* Check the parameters */
  686. assert_param(IS_RCC_PCLK(RCC_HCLK));
  687. tmpreg = RCC->CFGR;
  688. /* Clear PPRE1[2:0] bits */
  689. tmpreg &= ~RCC_CFGR_PPRE1;
  690. /* Set PPRE1[2:0] bits according to RCC_HCLK value */
  691. tmpreg |= RCC_HCLK;
  692. /* Store the new value */
  693. RCC->CFGR = tmpreg;
  694. }
  695. /**
  696. * @brief Configures the High Speed APB clock (PCLK2).
  697. * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
  698. * the AHB clock (HCLK).
  699. * This parameter can be one of the following values:
  700. * @arg RCC_HCLK_Div1: APB2 clock = HCLK
  701. * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
  702. * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
  703. * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
  704. * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
  705. * @retval None
  706. */
  707. void RCC_PCLK2Config(uint32_t RCC_HCLK)
  708. {
  709. uint32_t tmpreg = 0;
  710. /* Check the parameters */
  711. assert_param(IS_RCC_PCLK(RCC_HCLK));
  712. tmpreg = RCC->CFGR;
  713. /* Clear PPRE2[2:0] bits */
  714. tmpreg &= ~RCC_CFGR_PPRE2;
  715. /* Set PPRE2[2:0] bits according to RCC_HCLK value */
  716. tmpreg |= RCC_HCLK << 3;
  717. /* Store the new value */
  718. RCC->CFGR = tmpreg;
  719. }
  720. /**
  721. * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK,
  722. * PCLK1 and PCLK2.
  723. *
  724. * @note The system frequency computed by this function is not the real
  725. * frequency in the chip. It is calculated based on the predefined
  726. * constant and the selected clock source:
  727. * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
  728. * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
  729. * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
  730. * or HSI_VALUE(*) multiplied/divided by the PLL factors.
  731. * @note (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
  732. * 16 MHz) but the real value may vary depending on the variations
  733. * in voltage and temperature.
  734. * @note (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
  735. * 25 MHz), user has to ensure that HSE_VALUE is same as the real
  736. * frequency of the crystal used. Otherwise, this function may
  737. * have wrong result.
  738. *
  739. * @note The result of this function could be not correct when using fractional
  740. * value for HSE crystal.
  741. *
  742. * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
  743. * the clocks frequencies.
  744. *
  745. * @note This function can be used by the user application to compute the
  746. * baudrate for the communication peripherals or configure other parameters.
  747. * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
  748. * must be called to update the structure's field. Otherwise, any
  749. * configuration based on this function will be incorrect.
  750. *
  751. * @retval None
  752. */
  753. void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
  754. {
  755. uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
  756. /* Get SYSCLK source -------------------------------------------------------*/
  757. tmp = RCC->CFGR & RCC_CFGR_SWS;
  758. switch (tmp)
  759. {
  760. case 0x00: /* HSI used as system clock source */
  761. RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
  762. break;
  763. case 0x04: /* HSE used as system clock source */
  764. RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
  765. break;
  766. case 0x08: /* PLL used as system clock source */
  767. /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
  768. SYSCLK = PLL_VCO / PLLP
  769. */
  770. pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
  771. pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
  772. if (pllsource != 0)
  773. {
  774. /* HSE used as PLL clock source */
  775. pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
  776. }
  777. else
  778. {
  779. /* HSI used as PLL clock source */
  780. pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
  781. }
  782. pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
  783. RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
  784. break;
  785. default:
  786. RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
  787. break;
  788. }
  789. /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
  790. /* Get HCLK prescaler */
  791. tmp = RCC->CFGR & RCC_CFGR_HPRE;
  792. tmp = tmp >> 4;
  793. presc = APBAHBPrescTable[tmp];
  794. /* HCLK clock frequency */
  795. RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
  796. /* Get PCLK1 prescaler */
  797. tmp = RCC->CFGR & RCC_CFGR_PPRE1;
  798. tmp = tmp >> 10;
  799. presc = APBAHBPrescTable[tmp];
  800. /* PCLK1 clock frequency */
  801. RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
  802. /* Get PCLK2 prescaler */
  803. tmp = RCC->CFGR & RCC_CFGR_PPRE2;
  804. tmp = tmp >> 13;
  805. presc = APBAHBPrescTable[tmp];
  806. /* PCLK2 clock frequency */
  807. RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
  808. }
  809. /**
  810. * @}
  811. */
  812. /** @defgroup RCC_Group3 Peripheral clocks configuration functions
  813. * @brief Peripheral clocks configuration functions
  814. *
  815. @verbatim
  816. ===============================================================================
  817. Peripheral clocks configuration functions
  818. ===============================================================================
  819. This section provide functions allowing to configure the Peripheral clocks.
  820. 1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31.
  821. 2. After restart from Reset or wakeup from STANDBY, all peripherals are off
  822. except internal SRAM, Flash and JTAG. Before to start using a peripheral you
  823. have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd()
  824. , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
  825. 3. To reset the peripherals configuration (to the default state after device reset)
  826. you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
  827. RCC_APB1PeriphResetCmd() functions.
  828. 4. To further reduce power consumption in SLEEP mode the peripheral clocks can
  829. be disabled prior to executing the WFI or WFE instructions. You can do this
  830. using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and
  831. RCC_APB1PeriphClockLPModeCmd() functions.
  832. @endverbatim
  833. * @{
  834. */
  835. /**
  836. * @brief Configures the RTC clock (RTCCLK).
  837. * @note As the RTC clock configuration bits are in the Backup domain and write
  838. * access is denied to this domain after reset, you have to enable write
  839. * access using PWR_BackupAccessCmd(ENABLE) function before to configure
  840. * the RTC clock source (to be done once after reset).
  841. * @note Once the RTC clock is configured it can't be changed unless the
  842. * Backup domain is reset using RCC_BackupResetCmd() function, or by
  843. * a Power On Reset (POR).
  844. *
  845. * @param RCC_RTCCLKSource: specifies the RTC clock source.
  846. * This parameter can be one of the following values:
  847. * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
  848. * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
  849. * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected
  850. * as RTC clock, where x:[2,31]
  851. *
  852. * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
  853. * work in STOP and STANDBY modes, and can be used as wakeup source.
  854. * However, when the HSE clock is used as RTC clock source, the RTC
  855. * cannot be used in STOP and STANDBY modes.
  856. * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
  857. * RTC clock source).
  858. *
  859. * @retval None
  860. */
  861. void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
  862. {
  863. uint32_t tmpreg = 0;
  864. /* Check the parameters */
  865. assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
  866. if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
  867. { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
  868. tmpreg = RCC->CFGR;
  869. /* Clear RTCPRE[4:0] bits */
  870. tmpreg &= ~RCC_CFGR_RTCPRE;
  871. /* Configure HSE division factor for RTC clock */
  872. tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
  873. /* Store the new value */
  874. RCC->CFGR = tmpreg;
  875. }
  876. /* Select the RTC clock source */
  877. RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
  878. }
  879. /**
  880. * @brief Enables or disables the RTC clock.
  881. * @note This function must be used only after the RTC clock source was selected
  882. * using the RCC_RTCCLKConfig function.
  883. * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
  884. * @retval None
  885. */
  886. void RCC_RTCCLKCmd(FunctionalState NewState)
  887. {
  888. /* Check the parameters */
  889. assert_param(IS_FUNCTIONAL_STATE(NewState));
  890. *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
  891. }
  892. /**
  893. * @brief Forces or releases the Backup domain reset.
  894. * @note This function resets the RTC peripheral (including the backup registers)
  895. * and the RTC clock source selection in RCC_CSR register.
  896. * @note The BKPSRAM is not affected by this reset.
  897. * @param NewState: new state of the Backup domain reset.
  898. * This parameter can be: ENABLE or DISABLE.
  899. * @retval None
  900. */
  901. void RCC_BackupResetCmd(FunctionalState NewState)
  902. {
  903. /* Check the parameters */
  904. assert_param(IS_FUNCTIONAL_STATE(NewState));
  905. *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
  906. }
  907. /**
  908. * @brief Configures the I2S clock source (I2SCLK).
  909. *
  910. * @note This function must be called before enabling the I2S APB clock.
  911. * @note This function applies only to Silicon RevisionB and RevisionY.
  912. *
  913. * @param RCC_I2SCLKSource: specifies the I2S clock source.
  914. * This parameter can be one of the following values:
  915. * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
  916. * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
  917. * used as I2S clock source
  918. * @retval None
  919. */
  920. void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
  921. {
  922. /* Check the parameters */
  923. assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
  924. *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
  925. }
  926. /**
  927. * @brief Enables or disables the AHB1 peripheral clock.
  928. * @note After reset, the peripheral clock (used for registers read/write access)
  929. * is disabled and the application software has to enable this clock before
  930. * using it.
  931. * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
  932. * This parameter can be any combination of the following values:
  933. * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
  934. * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
  935. * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
  936. * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
  937. * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
  938. * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
  939. * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
  940. * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
  941. * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
  942. * @arg RCC_AHB1Periph_CRC: CRC clock
  943. * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
  944. * @arg RCC_AHB1Periph_DMA1: DMA1 clock
  945. * @arg RCC_AHB1Periph_DMA2: DMA2 clock
  946. * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
  947. * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
  948. * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
  949. * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
  950. * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
  951. * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
  952. * @param NewState: new state of the specified peripheral clock.
  953. * This parameter can be: ENABLE or DISABLE.
  954. * @retval None
  955. */
  956. void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
  957. {
  958. /* Check the parameters */
  959. assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
  960. assert_param(IS_FUNCTIONAL_STATE(NewState));
  961. if (NewState != DISABLE)
  962. {
  963. RCC->AHB1ENR |= RCC_AHB1Periph;
  964. }
  965. else
  966. {
  967. RCC->AHB1ENR &= ~RCC_AHB1Periph;
  968. }
  969. }
  970. /**
  971. * @brief Enables or disables the AHB2 peripheral clock.
  972. * @note After reset, the peripheral clock (used for registers read/write access)
  973. * is disabled and the application software has to enable this clock before
  974. * using it.
  975. * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
  976. * This parameter can be any combination of the following values:
  977. * @arg RCC_AHB2Periph_DCMI: DCMI clock
  978. * @arg RCC_AHB2Periph_CRYP: CRYP clock
  979. * @arg RCC_AHB2Periph_HASH: HASH clock
  980. * @arg RCC_AHB2Periph_RNG: RNG clock
  981. * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
  982. * @param NewState: new state of the specified peripheral clock.
  983. * This parameter can be: ENABLE or DISABLE.
  984. * @retval None
  985. */
  986. void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
  987. {
  988. /* Check the parameters */
  989. assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
  990. assert_param(IS_FUNCTIONAL_STATE(NewState));
  991. if (NewState != DISABLE)
  992. {
  993. RCC->AHB2ENR |= RCC_AHB2Periph;
  994. }
  995. else
  996. {
  997. RCC->AHB2ENR &= ~RCC_AHB2Periph;
  998. }
  999. }
  1000. /**
  1001. * @brief Enables or disables the AHB3 peripheral clock.
  1002. * @note After reset, the peripheral clock (used for registers read/write access)
  1003. * is disabled and the application software has to enable this clock before
  1004. * using it.
  1005. * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
  1006. * This parameter must be: RCC_AHB3Periph_FSMC
  1007. * @param NewState: new state of the specified peripheral clock.
  1008. * This parameter can be: ENABLE or DISABLE.
  1009. * @retval None
  1010. */
  1011. void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
  1012. {
  1013. /* Check the parameters */
  1014. assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
  1015. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1016. if (NewState != DISABLE)
  1017. {
  1018. RCC->AHB3ENR |= RCC_AHB3Periph;
  1019. }
  1020. else
  1021. {
  1022. RCC->AHB3ENR &= ~RCC_AHB3Periph;
  1023. }
  1024. }
  1025. /**
  1026. * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
  1027. * @note After reset, the peripheral clock (used for registers read/write access)
  1028. * is disabled and the application software has to enable this clock before
  1029. * using it.
  1030. * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
  1031. * This parameter can be any combination of the following values:
  1032. * @arg RCC_APB1Periph_TIM2: TIM2 clock
  1033. * @arg RCC_APB1Periph_TIM3: TIM3 clock
  1034. * @arg RCC_APB1Periph_TIM4: TIM4 clock
  1035. * @arg RCC_APB1Periph_TIM5: TIM5 clock
  1036. * @arg RCC_APB1Periph_TIM6: TIM6 clock
  1037. * @arg RCC_APB1Periph_TIM7: TIM7 clock
  1038. * @arg RCC_APB1Periph_TIM12: TIM12 clock
  1039. * @arg RCC_APB1Periph_TIM13: TIM13 clock
  1040. * @arg RCC_APB1Periph_TIM14: TIM14 clock
  1041. * @arg RCC_APB1Periph_WWDG: WWDG clock
  1042. * @arg RCC_APB1Periph_SPI2: SPI2 clock
  1043. * @arg RCC_APB1Periph_SPI3: SPI3 clock
  1044. * @arg RCC_APB1Periph_USART2: USART2 clock
  1045. * @arg RCC_APB1Periph_USART3: USART3 clock
  1046. * @arg RCC_APB1Periph_UART4: UART4 clock
  1047. * @arg RCC_APB1Periph_UART5: UART5 clock
  1048. * @arg RCC_APB1Periph_I2C1: I2C1 clock
  1049. * @arg RCC_APB1Periph_I2C2: I2C2 clock
  1050. * @arg RCC_APB1Periph_I2C3: I2C3 clock
  1051. * @arg RCC_APB1Periph_CAN1: CAN1 clock
  1052. * @arg RCC_APB1Periph_CAN2: CAN2 clock
  1053. * @arg RCC_APB1Periph_PWR: PWR clock
  1054. * @arg RCC_APB1Periph_DAC: DAC clock
  1055. * @param NewState: new state of the specified peripheral clock.
  1056. * This parameter can be: ENABLE or DISABLE.
  1057. * @retval None
  1058. */
  1059. void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
  1060. {
  1061. /* Check the parameters */
  1062. assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
  1063. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1064. if (NewState != DISABLE)
  1065. {
  1066. RCC->APB1ENR |= RCC_APB1Periph;
  1067. }
  1068. else
  1069. {
  1070. RCC->APB1ENR &= ~RCC_APB1Periph;
  1071. }
  1072. }
  1073. /**
  1074. * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
  1075. * @note After reset, the peripheral clock (used for registers read/write access)
  1076. * is disabled and the application software has to enable this clock before
  1077. * using it.
  1078. * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
  1079. * This parameter can be any combination of the following values:
  1080. * @arg RCC_APB2Periph_TIM1: TIM1 clock
  1081. * @arg RCC_APB2Periph_TIM8: TIM8 clock
  1082. * @arg RCC_APB2Periph_USART1: USART1 clock
  1083. * @arg RCC_APB2Periph_USART6: USART6 clock
  1084. * @arg RCC_APB2Periph_ADC1: ADC1 clock
  1085. * @arg RCC_APB2Periph_ADC2: ADC2 clock
  1086. * @arg RCC_APB2Periph_ADC3: ADC3 clock
  1087. * @arg RCC_APB2Periph_SDIO: SDIO clock
  1088. * @arg RCC_APB2Periph_SPI1: SPI1 clock
  1089. * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
  1090. * @arg RCC_APB2Periph_TIM9: TIM9 clock
  1091. * @arg RCC_APB2Periph_TIM10: TIM10 clock
  1092. * @arg RCC_APB2Periph_TIM11: TIM11 clock
  1093. * @param NewState: new state of the specified peripheral clock.
  1094. * This parameter can be: ENABLE or DISABLE.
  1095. * @retval None
  1096. */
  1097. void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
  1098. {
  1099. /* Check the parameters */
  1100. assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
  1101. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1102. if (NewState != DISABLE)
  1103. {
  1104. RCC->APB2ENR |= RCC_APB2Periph;
  1105. }
  1106. else
  1107. {
  1108. RCC->APB2ENR &= ~RCC_APB2Periph;
  1109. }
  1110. }
  1111. /**
  1112. * @brief Forces or releases AHB1 peripheral reset.
  1113. * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset.
  1114. * This parameter can be any combination of the following values:
  1115. * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
  1116. * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
  1117. * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
  1118. * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
  1119. * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
  1120. * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
  1121. * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
  1122. * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
  1123. * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
  1124. * @arg RCC_AHB1Periph_CRC: CRC clock
  1125. * @arg RCC_AHB1Periph_DMA1: DMA1 clock
  1126. * @arg RCC_AHB1Periph_DMA2: DMA2 clock
  1127. * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
  1128. * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
  1129. *
  1130. * @param NewState: new state of the specified peripheral reset.
  1131. * This parameter can be: ENABLE or DISABLE.
  1132. * @retval None
  1133. */
  1134. void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
  1135. {
  1136. /* Check the parameters */
  1137. assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
  1138. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1139. if (NewState != DISABLE)
  1140. {
  1141. RCC->AHB1RSTR |= RCC_AHB1Periph;
  1142. }
  1143. else
  1144. {
  1145. RCC->AHB1RSTR &= ~RCC_AHB1Periph;
  1146. }
  1147. }
  1148. /**
  1149. * @brief Forces or releases AHB2 peripheral reset.
  1150. * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset.
  1151. * This parameter can be any combination of the following values:
  1152. * @arg RCC_AHB2Periph_DCMI: DCMI clock
  1153. * @arg RCC_AHB2Periph_CRYP: CRYP clock
  1154. * @arg RCC_AHB2Periph_HASH: HASH clock
  1155. * @arg RCC_AHB2Periph_RNG: RNG clock
  1156. * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
  1157. * @param NewState: new state of the specified peripheral reset.
  1158. * This parameter can be: ENABLE or DISABLE.
  1159. * @retval None
  1160. */
  1161. void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
  1162. {
  1163. /* Check the parameters */
  1164. assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
  1165. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1166. if (NewState != DISABLE)
  1167. {
  1168. RCC->AHB2RSTR |= RCC_AHB2Periph;
  1169. }
  1170. else
  1171. {
  1172. RCC->AHB2RSTR &= ~RCC_AHB2Periph;
  1173. }
  1174. }
  1175. /**
  1176. * @brief Forces or releases AHB3 peripheral reset.
  1177. * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
  1178. * This parameter must be: RCC_AHB3Periph_FSMC
  1179. * @param NewState: new state of the specified peripheral reset.
  1180. * This parameter can be: ENABLE or DISABLE.
  1181. * @retval None
  1182. */
  1183. void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
  1184. {
  1185. /* Check the parameters */
  1186. assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
  1187. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1188. if (NewState != DISABLE)
  1189. {
  1190. RCC->AHB3RSTR |= RCC_AHB3Periph;
  1191. }
  1192. else
  1193. {
  1194. RCC->AHB3RSTR &= ~RCC_AHB3Periph;
  1195. }
  1196. }
  1197. /**
  1198. * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
  1199. * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
  1200. * This parameter can be any combination of the following values:
  1201. * @arg RCC_APB1Periph_TIM2: TIM2 clock
  1202. * @arg RCC_APB1Periph_TIM3: TIM3 clock
  1203. * @arg RCC_APB1Periph_TIM4: TIM4 clock
  1204. * @arg RCC_APB1Periph_TIM5: TIM5 clock
  1205. * @arg RCC_APB1Periph_TIM6: TIM6 clock
  1206. * @arg RCC_APB1Periph_TIM7: TIM7 clock
  1207. * @arg RCC_APB1Periph_TIM12: TIM12 clock
  1208. * @arg RCC_APB1Periph_TIM13: TIM13 clock
  1209. * @arg RCC_APB1Periph_TIM14: TIM14 clock
  1210. * @arg RCC_APB1Periph_WWDG: WWDG clock
  1211. * @arg RCC_APB1Periph_SPI2: SPI2 clock
  1212. * @arg RCC_APB1Periph_SPI3: SPI3 clock
  1213. * @arg RCC_APB1Periph_USART2: USART2 clock
  1214. * @arg RCC_APB1Periph_USART3: USART3 clock
  1215. * @arg RCC_APB1Periph_UART4: UART4 clock
  1216. * @arg RCC_APB1Periph_UART5: UART5 clock
  1217. * @arg RCC_APB1Periph_I2C1: I2C1 clock
  1218. * @arg RCC_APB1Periph_I2C2: I2C2 clock
  1219. * @arg RCC_APB1Periph_I2C3: I2C3 clock
  1220. * @arg RCC_APB1Periph_CAN1: CAN1 clock
  1221. * @arg RCC_APB1Periph_CAN2: CAN2 clock
  1222. * @arg RCC_APB1Periph_PWR: PWR clock
  1223. * @arg RCC_APB1Periph_DAC: DAC clock
  1224. * @param NewState: new state of the specified peripheral reset.
  1225. * This parameter can be: ENABLE or DISABLE.
  1226. * @retval None
  1227. */
  1228. void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
  1229. {
  1230. /* Check the parameters */
  1231. assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
  1232. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1233. if (NewState != DISABLE)
  1234. {
  1235. RCC->APB1RSTR |= RCC_APB1Periph;
  1236. }
  1237. else
  1238. {
  1239. RCC->APB1RSTR &= ~RCC_APB1Periph;
  1240. }
  1241. }
  1242. /**
  1243. * @brief Forces or releases High Speed APB (APB2) peripheral reset.
  1244. * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
  1245. * This parameter can be any combination of the following values:
  1246. * @arg RCC_APB2Periph_TIM1: TIM1 clock
  1247. * @arg RCC_APB2Periph_TIM8: TIM8 clock
  1248. * @arg RCC_APB2Periph_USART1: USART1 clock
  1249. * @arg RCC_APB2Periph_USART6: USART6 clock
  1250. * @arg RCC_APB2Periph_ADC1: ADC1 clock
  1251. * @arg RCC_APB2Periph_ADC2: ADC2 clock
  1252. * @arg RCC_APB2Periph_ADC3: ADC3 clock
  1253. * @arg RCC_APB2Periph_SDIO: SDIO clock
  1254. * @arg RCC_APB2Periph_SPI1: SPI1 clock
  1255. * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
  1256. * @arg RCC_APB2Periph_TIM9: TIM9 clock
  1257. * @arg RCC_APB2Periph_TIM10: TIM10 clock
  1258. * @arg RCC_APB2Periph_TIM11: TIM11 clock
  1259. * @param NewState: new state of the specified peripheral reset.
  1260. * This parameter can be: ENABLE or DISABLE.
  1261. * @retval None
  1262. */
  1263. void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
  1264. {
  1265. /* Check the parameters */
  1266. assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
  1267. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1268. if (NewState != DISABLE)
  1269. {
  1270. RCC->APB2RSTR |= RCC_APB2Periph;
  1271. }
  1272. else
  1273. {
  1274. RCC->APB2RSTR &= ~RCC_APB2Periph;
  1275. }
  1276. }
  1277. /**
  1278. * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
  1279. * @note Peripheral clock gating in SLEEP mode can be used to further reduce
  1280. * power consumption.
  1281. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
  1282. * @note By default, all peripheral clocks are enabled during SLEEP mode.
  1283. * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
  1284. * This parameter can be any combination of the following values:
  1285. * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
  1286. * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
  1287. * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
  1288. * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
  1289. * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
  1290. * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
  1291. * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
  1292. * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
  1293. * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
  1294. * @arg RCC_AHB1Periph_CRC: CRC clock
  1295. * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
  1296. * @arg RCC_AHB1Periph_DMA1: DMA1 clock
  1297. * @arg RCC_AHB1Periph_DMA2: DMA2 clock
  1298. * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
  1299. * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
  1300. * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
  1301. * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
  1302. * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
  1303. * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
  1304. * @param NewState: new state of the specified peripheral clock.
  1305. * This parameter can be: ENABLE or DISABLE.
  1306. * @retval None
  1307. */
  1308. void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
  1309. {
  1310. /* Check the parameters */
  1311. assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
  1312. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1313. if (NewState != DISABLE)
  1314. {
  1315. RCC->AHB1LPENR |= RCC_AHB1Periph;
  1316. }
  1317. else
  1318. {
  1319. RCC->AHB1LPENR &= ~RCC_AHB1Periph;
  1320. }
  1321. }
  1322. /**
  1323. * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
  1324. * @note Peripheral clock gating in SLEEP mode can be used to further reduce
  1325. * power consumption.
  1326. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
  1327. * @note By default, all peripheral clocks are enabled during SLEEP mode.
  1328. * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
  1329. * This parameter can be any combination of the following values:
  1330. * @arg RCC_AHB2Periph_DCMI: DCMI clock
  1331. * @arg RCC_AHB2Periph_CRYP: CRYP clock
  1332. * @arg RCC_AHB2Periph_HASH: HASH clock
  1333. * @arg RCC_AHB2Periph_RNG: RNG clock
  1334. * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
  1335. * @param NewState: new state of the specified peripheral clock.
  1336. * This parameter can be: ENABLE or DISABLE.
  1337. * @retval None
  1338. */
  1339. void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
  1340. {
  1341. /* Check the parameters */
  1342. assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
  1343. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1344. if (NewState != DISABLE)
  1345. {
  1346. RCC->AHB2LPENR |= RCC_AHB2Periph;
  1347. }
  1348. else
  1349. {
  1350. RCC->AHB2LPENR &= ~RCC_AHB2Periph;
  1351. }
  1352. }
  1353. /**
  1354. * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
  1355. * @note Peripheral clock gating in SLEEP mode can be used to further reduce
  1356. * power consumption.
  1357. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
  1358. * @note By default, all peripheral clocks are enabled during SLEEP mode.
  1359. * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
  1360. * This parameter must be: RCC_AHB3Periph_FSMC
  1361. * @param NewState: new state of the specified peripheral clock.
  1362. * This parameter can be: ENABLE or DISABLE.
  1363. * @retval None
  1364. */
  1365. void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
  1366. {
  1367. /* Check the parameters */
  1368. assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
  1369. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1370. if (NewState != DISABLE)
  1371. {
  1372. RCC->AHB3LPENR |= RCC_AHB3Periph;
  1373. }
  1374. else
  1375. {
  1376. RCC->AHB3LPENR &= ~RCC_AHB3Periph;
  1377. }
  1378. }
  1379. /**
  1380. * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
  1381. * @note Peripheral clock gating in SLEEP mode can be used to further reduce
  1382. * power consumption.
  1383. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
  1384. * @note By default, all peripheral clocks are enabled during SLEEP mode.
  1385. * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
  1386. * This parameter can be any combination of the following values:
  1387. * @arg RCC_APB1Periph_TIM2: TIM2 clock
  1388. * @arg RCC_APB1Periph_TIM3: TIM3 clock
  1389. * @arg RCC_APB1Periph_TIM4: TIM4 clock
  1390. * @arg RCC_APB1Periph_TIM5: TIM5 clock
  1391. * @arg RCC_APB1Periph_TIM6: TIM6 clock
  1392. * @arg RCC_APB1Periph_TIM7: TIM7 clock
  1393. * @arg RCC_APB1Periph_TIM12: TIM12 clock
  1394. * @arg RCC_APB1Periph_TIM13: TIM13 clock
  1395. * @arg RCC_APB1Periph_TIM14: TIM14 clock
  1396. * @arg RCC_APB1Periph_WWDG: WWDG clock
  1397. * @arg RCC_APB1Periph_SPI2: SPI2 clock
  1398. * @arg RCC_APB1Periph_SPI3: SPI3 clock
  1399. * @arg RCC_APB1Periph_USART2: USART2 clock
  1400. * @arg RCC_APB1Periph_USART3: USART3 clock
  1401. * @arg RCC_APB1Periph_UART4: UART4 clock
  1402. * @arg RCC_APB1Periph_UART5: UART5 clock
  1403. * @arg RCC_APB1Periph_I2C1: I2C1 clock
  1404. * @arg RCC_APB1Periph_I2C2: I2C2 clock
  1405. * @arg RCC_APB1Periph_I2C3: I2C3 clock
  1406. * @arg RCC_APB1Periph_CAN1: CAN1 clock
  1407. * @arg RCC_APB1Periph_CAN2: CAN2 clock
  1408. * @arg RCC_APB1Periph_PWR: PWR clock
  1409. * @arg RCC_APB1Periph_DAC: DAC clock
  1410. * @param NewState: new state of the specified peripheral clock.
  1411. * This parameter can be: ENABLE or DISABLE.
  1412. * @retval None
  1413. */
  1414. void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
  1415. {
  1416. /* Check the parameters */
  1417. assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
  1418. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1419. if (NewState != DISABLE)
  1420. {
  1421. RCC->APB1LPENR |= RCC_APB1Periph;
  1422. }
  1423. else
  1424. {
  1425. RCC->APB1LPENR &= ~RCC_APB1Periph;
  1426. }
  1427. }
  1428. /**
  1429. * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
  1430. * @note Peripheral clock gating in SLEEP mode can be used to further reduce
  1431. * power consumption.
  1432. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
  1433. * @note By default, all peripheral clocks are enabled during SLEEP mode.
  1434. * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
  1435. * This parameter can be any combination of the following values:
  1436. * @arg RCC_APB2Periph_TIM1: TIM1 clock
  1437. * @arg RCC_APB2Periph_TIM8: TIM8 clock
  1438. * @arg RCC_APB2Periph_USART1: USART1 clock
  1439. * @arg RCC_APB2Periph_USART6: USART6 clock
  1440. * @arg RCC_APB2Periph_ADC1: ADC1 clock
  1441. * @arg RCC_APB2Periph_ADC2: ADC2 clock
  1442. * @arg RCC_APB2Periph_ADC3: ADC3 clock
  1443. * @arg RCC_APB2Periph_SDIO: SDIO clock
  1444. * @arg RCC_APB2Periph_SPI1: SPI1 clock
  1445. * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
  1446. * @arg RCC_APB2Periph_TIM9: TIM9 clock
  1447. * @arg RCC_APB2Periph_TIM10: TIM10 clock
  1448. * @arg RCC_APB2Periph_TIM11: TIM11 clock
  1449. * @param NewState: new state of the specified peripheral clock.
  1450. * This parameter can be: ENABLE or DISABLE.
  1451. * @retval None
  1452. */
  1453. void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
  1454. {
  1455. /* Check the parameters */
  1456. assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
  1457. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1458. if (NewState != DISABLE)
  1459. {
  1460. RCC->APB2LPENR |= RCC_APB2Periph;
  1461. }
  1462. else
  1463. {
  1464. RCC->APB2LPENR &= ~RCC_APB2Periph;
  1465. }
  1466. }
  1467. /**
  1468. * @}
  1469. */
  1470. /** @defgroup RCC_Group4 Interrupts and flags management functions
  1471. * @brief Interrupts and flags management functions
  1472. *
  1473. @verbatim
  1474. ===============================================================================
  1475. Interrupts and flags management functions
  1476. ===============================================================================
  1477. @endverbatim
  1478. * @{
  1479. */
  1480. /**
  1481. * @brief Enables or disables the specified RCC interrupts.
  1482. * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
  1483. * This parameter can be any combination of the following values:
  1484. * @arg RCC_IT_LSIRDY: LSI ready interrupt
  1485. * @arg RCC_IT_LSERDY: LSE ready interrupt
  1486. * @arg RCC_IT_HSIRDY: HSI ready interrupt
  1487. * @arg RCC_IT_HSERDY: HSE ready interrupt
  1488. * @arg RCC_IT_PLLRDY: main PLL ready interrupt
  1489. * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
  1490. * @param NewState: new state of the specified RCC interrupts.
  1491. * This parameter can be: ENABLE or DISABLE.
  1492. * @retval None
  1493. */
  1494. void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
  1495. {
  1496. /* Check the parameters */
  1497. assert_param(IS_RCC_IT(RCC_IT));
  1498. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1499. if (NewState != DISABLE)
  1500. {
  1501. /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
  1502. *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
  1503. }
  1504. else
  1505. {
  1506. /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
  1507. *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
  1508. }
  1509. }
  1510. /**
  1511. * @brief Checks whether the specified RCC flag is set or not.
  1512. * @param RCC_FLAG: specifies the flag to check.
  1513. * This parameter can be one of the following values:
  1514. * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
  1515. * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
  1516. * @arg RCC_FLAG_PLLRDY: main PLL clock ready
  1517. * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
  1518. * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
  1519. * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
  1520. * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset
  1521. * @arg RCC_FLAG_PINRST: Pin reset
  1522. * @arg RCC_FLAG_PORRST: POR/PDR reset
  1523. * @arg RCC_FLAG_SFTRST: Software reset
  1524. * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
  1525. * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
  1526. * @arg RCC_FLAG_LPWRRST: Low Power reset
  1527. * @retval The new state of RCC_FLAG (SET or RESET).
  1528. */
  1529. FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
  1530. {
  1531. uint32_t tmp = 0;
  1532. uint32_t statusreg = 0;
  1533. FlagStatus bitstatus = RESET;
  1534. /* Check the parameters */
  1535. assert_param(IS_RCC_FLAG(RCC_FLAG));
  1536. /* Get the RCC register index */
  1537. tmp = RCC_FLAG >> 5;
  1538. if (tmp == 1) /* The flag to check is in CR register */
  1539. {
  1540. statusreg = RCC->CR;
  1541. }
  1542. else if (tmp == 2) /* The flag to check is in BDCR register */
  1543. {
  1544. statusreg = RCC->BDCR;
  1545. }
  1546. else /* The flag to check is in CSR register */
  1547. {
  1548. statusreg = RCC->CSR;
  1549. }
  1550. /* Get the flag position */
  1551. tmp = RCC_FLAG & FLAG_MASK;
  1552. if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
  1553. {
  1554. bitstatus = SET;
  1555. }
  1556. else
  1557. {
  1558. bitstatus = RESET;
  1559. }
  1560. /* Return the flag status */
  1561. return bitstatus;
  1562. }
  1563. /**
  1564. * @brief Clears the RCC reset flags.
  1565. * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
  1566. * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
  1567. * @param None
  1568. * @retval None
  1569. */
  1570. void RCC_ClearFlag(void)
  1571. {
  1572. /* Set RMVF bit to clear the reset flags */
  1573. RCC->CSR |= RCC_CSR_RMVF;
  1574. }
  1575. /**
  1576. * @brief Checks whether the specified RCC interrupt has occurred or not.
  1577. * @param RCC_IT: specifies the RCC interrupt source to check.
  1578. * This parameter can be one of the following values:
  1579. * @arg RCC_IT_LSIRDY: LSI ready interrupt
  1580. * @arg RCC_IT_LSERDY: LSE ready interrupt
  1581. * @arg RCC_IT_HSIRDY: HSI ready interrupt
  1582. * @arg RCC_IT_HSERDY: HSE ready interrupt
  1583. * @arg RCC_IT_PLLRDY: main PLL ready interrupt
  1584. * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
  1585. * @arg RCC_IT_CSS: Clock Security System interrupt
  1586. * @retval The new state of RCC_IT (SET or RESET).
  1587. */
  1588. ITStatus RCC_GetITStatus(uint8_t RCC_IT)
  1589. {
  1590. ITStatus bitstatus = RESET;
  1591. /* Check the parameters */
  1592. assert_param(IS_RCC_GET_IT(RCC_IT));
  1593. /* Check the status of the specified RCC interrupt */
  1594. if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
  1595. {
  1596. bitstatus = SET;
  1597. }
  1598. else
  1599. {
  1600. bitstatus = RESET;
  1601. }
  1602. /* Return the RCC_IT status */
  1603. return bitstatus;
  1604. }
  1605. /**
  1606. * @brief Clears the RCC's interrupt pending bits.
  1607. * @param RCC_IT: specifies the interrupt pending bit to clear.
  1608. * This parameter can be any combination of the following values:
  1609. * @arg RCC_IT_LSIRDY: LSI ready interrupt
  1610. * @arg RCC_IT_LSERDY: LSE ready interrupt
  1611. * @arg RCC_IT_HSIRDY: HSI ready interrupt
  1612. * @arg RCC_IT_HSERDY: HSE ready interrupt
  1613. * @arg RCC_IT_PLLRDY: main PLL ready interrupt
  1614. * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
  1615. * @arg RCC_IT_CSS: Clock Security System interrupt
  1616. * @retval None
  1617. */
  1618. void RCC_ClearITPendingBit(uint8_t RCC_IT)
  1619. {
  1620. /* Check the parameters */
  1621. assert_param(IS_RCC_CLEAR_IT(RCC_IT));
  1622. /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
  1623. pending bits */
  1624. *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
  1625. }
  1626. /**
  1627. * @}
  1628. */
  1629. /**
  1630. * @}
  1631. */
  1632. /**
  1633. * @}
  1634. */
  1635. /**
  1636. * @}
  1637. */