core_cmFunc.h 15 KB

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  1. /**************************************************************************//**
  2. * @file core_cmFunc.h
  3. * @brief CMSIS Cortex-M Core Function Access Header File
  4. * @version V2.10
  5. * @date 26. July 2011
  6. *
  7. * @note
  8. * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  9. *
  10. * @par
  11. * ARM Limited (ARM) is supplying this software for use with Cortex-M
  12. * processor based microcontrollers. This file can be freely distributed
  13. * within development tools that are supporting such ARM based processors.
  14. *
  15. * @par
  16. * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  17. * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  18. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  19. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  20. * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  21. *
  22. ******************************************************************************/
  23. #ifndef __CORE_CMFUNC_H
  24. #define __CORE_CMFUNC_H
  25. /* ########################### Core Function Access ########################### */
  26. /** \ingroup CMSIS_Core_FunctionInterface
  27. \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
  28. @{
  29. */
  30. #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
  31. /* ARM armcc specific functions */
  32. #if (__ARMCC_VERSION < 400677)
  33. #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
  34. #endif
  35. /* intrinsic void __enable_irq(); */
  36. /* intrinsic void __disable_irq(); */
  37. /** \brief Get Control Register
  38. This function returns the content of the Control Register.
  39. \return Control Register value
  40. */
  41. static __INLINE uint32_t __get_CONTROL(void)
  42. {
  43. register uint32_t __regControl __ASM("control");
  44. return(__regControl);
  45. }
  46. /** \brief Set Control Register
  47. This function writes the given value to the Control Register.
  48. \param [in] control Control Register value to set
  49. */
  50. static __INLINE void __set_CONTROL(uint32_t control)
  51. {
  52. register uint32_t __regControl __ASM("control");
  53. __regControl = control;
  54. }
  55. /** \brief Get ISPR Register
  56. This function returns the content of the ISPR Register.
  57. \return ISPR Register value
  58. */
  59. static __INLINE uint32_t __get_IPSR(void)
  60. {
  61. register uint32_t __regIPSR __ASM("ipsr");
  62. return(__regIPSR);
  63. }
  64. /** \brief Get APSR Register
  65. This function returns the content of the APSR Register.
  66. \return APSR Register value
  67. */
  68. static __INLINE uint32_t __get_APSR(void)
  69. {
  70. register uint32_t __regAPSR __ASM("apsr");
  71. return(__regAPSR);
  72. }
  73. /** \brief Get xPSR Register
  74. This function returns the content of the xPSR Register.
  75. \return xPSR Register value
  76. */
  77. static __INLINE uint32_t __get_xPSR(void)
  78. {
  79. register uint32_t __regXPSR __ASM("xpsr");
  80. return(__regXPSR);
  81. }
  82. /** \brief Get Process Stack Pointer
  83. This function returns the current value of the Process Stack Pointer (PSP).
  84. \return PSP Register value
  85. */
  86. static __INLINE uint32_t __get_PSP(void)
  87. {
  88. register uint32_t __regProcessStackPointer __ASM("psp");
  89. return(__regProcessStackPointer);
  90. }
  91. /** \brief Set Process Stack Pointer
  92. This function assigns the given value to the Process Stack Pointer (PSP).
  93. \param [in] topOfProcStack Process Stack Pointer value to set
  94. */
  95. static __INLINE void __set_PSP(uint32_t topOfProcStack)
  96. {
  97. register uint32_t __regProcessStackPointer __ASM("psp");
  98. __regProcessStackPointer = topOfProcStack;
  99. }
  100. /** \brief Get Main Stack Pointer
  101. This function returns the current value of the Main Stack Pointer (MSP).
  102. \return MSP Register value
  103. */
  104. static __INLINE uint32_t __get_MSP(void)
  105. {
  106. register uint32_t __regMainStackPointer __ASM("msp");
  107. return(__regMainStackPointer);
  108. }
  109. /** \brief Set Main Stack Pointer
  110. This function assigns the given value to the Main Stack Pointer (MSP).
  111. \param [in] topOfMainStack Main Stack Pointer value to set
  112. */
  113. static __INLINE void __set_MSP(uint32_t topOfMainStack)
  114. {
  115. register uint32_t __regMainStackPointer __ASM("msp");
  116. __regMainStackPointer = topOfMainStack;
  117. }
  118. /** \brief Get Priority Mask
  119. This function returns the current state of the priority mask bit from the Priority Mask Register.
  120. \return Priority Mask value
  121. */
  122. static __INLINE uint32_t __get_PRIMASK(void)
  123. {
  124. register uint32_t __regPriMask __ASM("primask");
  125. return(__regPriMask);
  126. }
  127. /** \brief Set Priority Mask
  128. This function assigns the given value to the Priority Mask Register.
  129. \param [in] priMask Priority Mask
  130. */
  131. static __INLINE void __set_PRIMASK(uint32_t priMask)
  132. {
  133. register uint32_t __regPriMask __ASM("primask");
  134. __regPriMask = (priMask);
  135. }
  136. #if (__CORTEX_M >= 0x03)
  137. /** \brief Enable FIQ
  138. This function enables FIQ interrupts by clearing the F-bit in the CPSR.
  139. Can only be executed in Privileged modes.
  140. */
  141. #define __enable_fault_irq __enable_fiq
  142. /** \brief Disable FIQ
  143. This function disables FIQ interrupts by setting the F-bit in the CPSR.
  144. Can only be executed in Privileged modes.
  145. */
  146. #define __disable_fault_irq __disable_fiq
  147. /** \brief Get Base Priority
  148. This function returns the current value of the Base Priority register.
  149. \return Base Priority register value
  150. */
  151. static __INLINE uint32_t __get_BASEPRI(void)
  152. {
  153. register uint32_t __regBasePri __ASM("basepri");
  154. return(__regBasePri);
  155. }
  156. /** \brief Set Base Priority
  157. This function assigns the given value to the Base Priority register.
  158. \param [in] basePri Base Priority value to set
  159. */
  160. static __INLINE void __set_BASEPRI(uint32_t basePri)
  161. {
  162. register uint32_t __regBasePri __ASM("basepri");
  163. __regBasePri = (basePri & 0xff);
  164. }
  165. /** \brief Get Fault Mask
  166. This function returns the current value of the Fault Mask register.
  167. \return Fault Mask register value
  168. */
  169. static __INLINE uint32_t __get_FAULTMASK(void)
  170. {
  171. register uint32_t __regFaultMask __ASM("faultmask");
  172. return(__regFaultMask);
  173. }
  174. /** \brief Set Fault Mask
  175. This function assigns the given value to the Fault Mask register.
  176. \param [in] faultMask Fault Mask value to set
  177. */
  178. static __INLINE void __set_FAULTMASK(uint32_t faultMask)
  179. {
  180. register uint32_t __regFaultMask __ASM("faultmask");
  181. __regFaultMask = (faultMask & (uint32_t)1);
  182. }
  183. #endif /* (__CORTEX_M >= 0x03) */
  184. #if (__CORTEX_M == 0x04)
  185. /** \brief Get FPSCR
  186. This function returns the current value of the Floating Point Status/Control register.
  187. \return Floating Point Status/Control register value
  188. */
  189. static __INLINE uint32_t __get_FPSCR(void)
  190. {
  191. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  192. register uint32_t __regfpscr __ASM("fpscr");
  193. return(__regfpscr);
  194. #else
  195. return(0);
  196. #endif
  197. }
  198. /** \brief Set FPSCR
  199. This function assigns the given value to the Floating Point Status/Control register.
  200. \param [in] fpscr Floating Point Status/Control value to set
  201. */
  202. static __INLINE void __set_FPSCR(uint32_t fpscr)
  203. {
  204. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  205. register uint32_t __regfpscr __ASM("fpscr");
  206. __regfpscr = (fpscr);
  207. #endif
  208. }
  209. #endif /* (__CORTEX_M == 0x04) */
  210. #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
  211. /* IAR iccarm specific functions */
  212. #include <cmsis_iar.h>
  213. #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
  214. /* GNU gcc specific functions */
  215. /** \brief Enable IRQ Interrupts
  216. This function enables IRQ interrupts by clearing the I-bit in the CPSR.
  217. Can only be executed in Privileged modes.
  218. */
  219. __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
  220. {
  221. __ASM volatile ("cpsie i");
  222. }
  223. /** \brief Disable IRQ Interrupts
  224. This function disables IRQ interrupts by setting the I-bit in the CPSR.
  225. Can only be executed in Privileged modes.
  226. */
  227. __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
  228. {
  229. __ASM volatile ("cpsid i");
  230. }
  231. /** \brief Get Control Register
  232. This function returns the content of the Control Register.
  233. \return Control Register value
  234. */
  235. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
  236. {
  237. uint32_t result;
  238. __ASM volatile ("MRS %0, control" : "=r" (result) );
  239. return(result);
  240. }
  241. /** \brief Set Control Register
  242. This function writes the given value to the Control Register.
  243. \param [in] control Control Register value to set
  244. */
  245. __attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
  246. {
  247. __ASM volatile ("MSR control, %0" : : "r" (control) );
  248. }
  249. /** \brief Get ISPR Register
  250. This function returns the content of the ISPR Register.
  251. \return ISPR Register value
  252. */
  253. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
  254. {
  255. uint32_t result;
  256. __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
  257. return(result);
  258. }
  259. /** \brief Get APSR Register
  260. This function returns the content of the APSR Register.
  261. \return APSR Register value
  262. */
  263. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
  264. {
  265. uint32_t result;
  266. __ASM volatile ("MRS %0, apsr" : "=r" (result) );
  267. return(result);
  268. }
  269. /** \brief Get xPSR Register
  270. This function returns the content of the xPSR Register.
  271. \return xPSR Register value
  272. */
  273. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
  274. {
  275. uint32_t result;
  276. __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
  277. return(result);
  278. }
  279. /** \brief Get Process Stack Pointer
  280. This function returns the current value of the Process Stack Pointer (PSP).
  281. \return PSP Register value
  282. */
  283. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
  284. {
  285. register uint32_t result;
  286. __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
  287. return(result);
  288. }
  289. /** \brief Set Process Stack Pointer
  290. This function assigns the given value to the Process Stack Pointer (PSP).
  291. \param [in] topOfProcStack Process Stack Pointer value to set
  292. */
  293. __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
  294. {
  295. __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
  296. }
  297. /** \brief Get Main Stack Pointer
  298. This function returns the current value of the Main Stack Pointer (MSP).
  299. \return MSP Register value
  300. */
  301. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
  302. {
  303. register uint32_t result;
  304. __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
  305. return(result);
  306. }
  307. /** \brief Set Main Stack Pointer
  308. This function assigns the given value to the Main Stack Pointer (MSP).
  309. \param [in] topOfMainStack Main Stack Pointer value to set
  310. */
  311. __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
  312. {
  313. __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
  314. }
  315. /** \brief Get Priority Mask
  316. This function returns the current state of the priority mask bit from the Priority Mask Register.
  317. \return Priority Mask value
  318. */
  319. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
  320. {
  321. uint32_t result;
  322. __ASM volatile ("MRS %0, primask" : "=r" (result) );
  323. return(result);
  324. }
  325. /** \brief Set Priority Mask
  326. This function assigns the given value to the Priority Mask Register.
  327. \param [in] priMask Priority Mask
  328. */
  329. __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
  330. {
  331. __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
  332. }
  333. #if (__CORTEX_M >= 0x03)
  334. /** \brief Enable FIQ
  335. This function enables FIQ interrupts by clearing the F-bit in the CPSR.
  336. Can only be executed in Privileged modes.
  337. */
  338. __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
  339. {
  340. __ASM volatile ("cpsie f");
  341. }
  342. /** \brief Disable FIQ
  343. This function disables FIQ interrupts by setting the F-bit in the CPSR.
  344. Can only be executed in Privileged modes.
  345. */
  346. __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
  347. {
  348. __ASM volatile ("cpsid f");
  349. }
  350. /** \brief Get Base Priority
  351. This function returns the current value of the Base Priority register.
  352. \return Base Priority register value
  353. */
  354. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
  355. {
  356. uint32_t result;
  357. __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
  358. return(result);
  359. }
  360. /** \brief Set Base Priority
  361. This function assigns the given value to the Base Priority register.
  362. \param [in] basePri Base Priority value to set
  363. */
  364. __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
  365. {
  366. __ASM volatile ("MSR basepri, %0" : : "r" (value) );
  367. }
  368. /** \brief Get Fault Mask
  369. This function returns the current value of the Fault Mask register.
  370. \return Fault Mask register value
  371. */
  372. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
  373. {
  374. uint32_t result;
  375. __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
  376. return(result);
  377. }
  378. /** \brief Set Fault Mask
  379. This function assigns the given value to the Fault Mask register.
  380. \param [in] faultMask Fault Mask value to set
  381. */
  382. __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
  383. {
  384. __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
  385. }
  386. #endif /* (__CORTEX_M >= 0x03) */
  387. #if (__CORTEX_M == 0x04)
  388. /** \brief Get FPSCR
  389. This function returns the current value of the Floating Point Status/Control register.
  390. \return Floating Point Status/Control register value
  391. */
  392. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
  393. {
  394. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  395. uint32_t result;
  396. __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
  397. return(result);
  398. #else
  399. return(0);
  400. #endif
  401. }
  402. /** \brief Set FPSCR
  403. This function assigns the given value to the Floating Point Status/Control register.
  404. \param [in] fpscr Floating Point Status/Control value to set
  405. */
  406. __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
  407. {
  408. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  409. __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
  410. #endif
  411. }
  412. #endif /* (__CORTEX_M == 0x04) */
  413. #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
  414. /* TASKING carm specific functions */
  415. /*
  416. * The CMSIS functions have been implemented as intrinsics in the compiler.
  417. * Please use "carm -?i" to get an up to date list of all instrinsics,
  418. * Including the CMSIS ones.
  419. */
  420. #endif
  421. /*@} end of CMSIS_Core_RegAccFunctions */
  422. #endif /* __CORE_CMFUNC_H */