stm32f2xx_spi.c 44 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f2xx_spi.c
  4. * @author MCD Application Team
  5. * @version V1.1.3
  6. * @date 31-December-2021
  7. * @brief This file provides firmware functions to manage the following
  8. * functionalities of the Serial peripheral interface (SPI):
  9. * - Initialization and Configuration
  10. * - Data transfers functions
  11. * - Hardware CRC Calculation
  12. * - DMA transfers management
  13. * - Interrupts and flags management
  14. *
  15. * @verbatim
  16. *
  17. *
  18. * ===================================================================
  19. * How to use this driver
  20. * ===================================================================
  21. * 1. Enable peripheral clock using the following functions
  22. * RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1
  23. * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2
  24. * RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3.
  25. *
  26. * 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd()
  27. * function.
  28. * In I2S mode, if an external clock source is used then the I2S CKIN pin GPIO
  29. * clock should also be enabled.
  30. *
  31. * 3. Peripherals alternate function:
  32. * - Connect the pin to the desired peripherals' Alternate
  33. * Function (AF) using GPIO_PinAFConfig() function
  34. * - Configure the desired pin in alternate function by:
  35. * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
  36. * - Select the type, pull-up/pull-down and output speed via
  37. * GPIO_PuPd, GPIO_OType and GPIO_Speed members
  38. * - Call GPIO_Init() function
  39. * In I2S mode, if an external clock source is used then the I2S CKIN pin
  40. * should be also configured in Alternate function Push-pull pull-up mode.
  41. *
  42. * 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
  43. * Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
  44. * function.
  45. * In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio
  46. * frequency and Polarity using I2S_Init() function.
  47. * For I2S mode, make sure that either:
  48. * - I2S PLL is configured using the functions RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S),
  49. * RCC_PLLI2SCmd(ENABLE) and RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY).
  50. * or
  51. * - External clock source is configured using the function
  52. * RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant
  53. * I2S_EXTERNAL_CLOCK_VAL in the stm32f2xx_conf.h file.
  54. *
  55. * 5. Enable the NVIC and the corresponding interrupt using the function
  56. * SPI_ITConfig() if you need to use interrupt mode.
  57. *
  58. * 6. When using the DMA mode
  59. * - Configure the DMA using DMA_Init() function
  60. * - Active the needed channel Request using SPI_I2S_DMACmd() function
  61. *
  62. * 7. Enable the SPI using the SPI_Cmd() function or enable the I2S using
  63. * I2S_Cmd().
  64. *
  65. * 8. Enable the DMA using the DMA_Cmd() function when using DMA mode.
  66. *
  67. * 9. Optionally, you can enable/configure the following parameters without
  68. * re-initialization (i.e there is no need to call again SPI_Init() function):
  69. * - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
  70. * is programmed as Data direction parameter using the SPI_Init() function
  71. * it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
  72. * using the SPI_BiDirectionalLineConfig() function.
  73. * - When SPI_NSS_Soft is selected as Slave Select Management parameter
  74. * using the SPI_Init() function it can be possible to manage the
  75. * NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
  76. * - Reconfigure the data size using the SPI_DataSizeConfig() function
  77. * - Enable or disable the SS output using the SPI_SSOutputCmd() function
  78. *
  79. * 10. To use the CRC Hardware calculation feature refer to the Peripheral
  80. * CRC hardware Calculation subsection.
  81. *
  82. *
  83. * @note This driver supports only the I2S clock scheme available in Silicon
  84. * RevisionB and RevisionY.
  85. *
  86. * @note In I2S mode: if an external clock is used as source clock for the I2S,
  87. * then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f2xx_conf.h should
  88. * be enabled and set to the value of the source clock frequency (in Hz).
  89. *
  90. * @note In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd()
  91. * just after calling the function SPI_Init().
  92. *
  93. * @endverbatim
  94. *
  95. ******************************************************************************
  96. * @attention
  97. *
  98. * Copyright (c) 2012 STMicroelectronics.
  99. * All rights reserved.
  100. *
  101. * This software is licensed under terms that can be found in the LICENSE file
  102. * in the root directory of this software component.
  103. * If no LICENSE file comes with this software, it is provided AS-IS.
  104. *
  105. ******************************************************************************
  106. */
  107. /* Includes ------------------------------------------------------------------*/
  108. #include "stm32f2xx_spi.h"
  109. #include "stm32f2xx_rcc.h"
  110. /** @addtogroup STM32F2xx_StdPeriph_Driver
  111. * @{
  112. */
  113. /** @defgroup SPI
  114. * @brief SPI driver modules
  115. * @{
  116. */
  117. /* Private typedef -----------------------------------------------------------*/
  118. /* Private define ------------------------------------------------------------*/
  119. /* SPI registers Masks */
  120. #define CR1_CLEAR_MASK ((uint16_t)0x3040)
  121. #define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040)
  122. /* RCC PLLs masks */
  123. #define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000)
  124. #define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0)
  125. #define SPI_CR2_FRF ((uint16_t)0x0010)
  126. #define SPI_SR_TIFRFE ((uint16_t)0x0100)
  127. /* Private macro -------------------------------------------------------------*/
  128. /* Private variables ---------------------------------------------------------*/
  129. /* Private function prototypes -----------------------------------------------*/
  130. /* Private functions ---------------------------------------------------------*/
  131. /** @defgroup SPI_Private_Functions
  132. * @{
  133. */
  134. /** @defgroup SPI_Group1 Initialization and Configuration functions
  135. * @brief Initialization and Configuration functions
  136. *
  137. @verbatim
  138. ===============================================================================
  139. Initialization and Configuration functions
  140. ===============================================================================
  141. This section provides a set of functions allowing to initialize the SPI Direction,
  142. SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
  143. Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
  144. The SPI_Init() function follows the SPI configuration procedures for Master mode
  145. and Slave mode (details for these procedures are available in reference manual
  146. (RM0033)).
  147. @endverbatim
  148. * @{
  149. */
  150. /**
  151. * @brief Deinitialize the SPIx peripheral registers to their default reset values.
  152. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
  153. * in SPI mode or 2 or 3 in I2S mode.
  154. * @retval None
  155. */
  156. void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
  157. {
  158. /* Check the parameters */
  159. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  160. if (SPIx == SPI1)
  161. {
  162. /* Enable SPI1 reset state */
  163. RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
  164. /* Release SPI1 from reset state */
  165. RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
  166. }
  167. else if (SPIx == SPI2)
  168. {
  169. /* Enable SPI2 reset state */
  170. RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
  171. /* Release SPI2 from reset state */
  172. RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
  173. }
  174. else
  175. {
  176. if (SPIx == SPI3)
  177. {
  178. /* Enable SPI3 reset state */
  179. RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
  180. /* Release SPI3 from reset state */
  181. RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
  182. }
  183. }
  184. }
  185. /**
  186. * @brief Initializes the SPIx peripheral according to the specified
  187. * parameters in the SPI_InitStruct.
  188. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
  189. * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
  190. * contains the configuration information for the specified SPI peripheral.
  191. * @retval None
  192. */
  193. void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
  194. {
  195. uint16_t tmpreg = 0;
  196. /* check the parameters */
  197. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  198. /* Check the SPI parameters */
  199. assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
  200. assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
  201. assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
  202. assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
  203. assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
  204. assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
  205. assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
  206. assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
  207. assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
  208. /*---------------------------- SPIx CR1 Configuration ------------------------*/
  209. /* Get the SPIx CR1 value */
  210. tmpreg = SPIx->CR1;
  211. /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
  212. tmpreg &= CR1_CLEAR_MASK;
  213. /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
  214. master/salve mode, CPOL and CPHA */
  215. /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
  216. /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
  217. /* Set LSBFirst bit according to SPI_FirstBit value */
  218. /* Set BR bits according to SPI_BaudRatePrescaler value */
  219. /* Set CPOL bit according to SPI_CPOL value */
  220. /* Set CPHA bit according to SPI_CPHA value */
  221. tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
  222. SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
  223. SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
  224. SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
  225. /* Write to SPIx CR1 */
  226. SPIx->CR1 = tmpreg;
  227. /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
  228. SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
  229. /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
  230. /* Write to SPIx CRCPOLY */
  231. SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
  232. }
  233. /**
  234. * @brief Initializes the SPIx peripheral according to the specified
  235. * parameters in the I2S_InitStruct.
  236. * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode).
  237. * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
  238. * contains the configuration information for the specified SPI peripheral
  239. * configured in I2S mode.
  240. *
  241. * @note The function calculates the optimal prescaler needed to obtain the most
  242. * accurate audio frequency (depending on the I2S clock source, the PLL values
  243. * and the product configuration). But in case the prescaler value is greater
  244. * than 511, the default value (0x02) will be configured instead.
  245. *
  246. * @note if an external clock is used as source clock for the I2S, then the define
  247. * I2S_EXTERNAL_CLOCK_VAL in file stm32f2xx_conf.h should be enabled and set
  248. * to the value of the the source clock frequency (in Hz).
  249. *
  250. * @retval None
  251. */
  252. void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
  253. {
  254. uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
  255. uint32_t tmp = 0, i2sclk = 0;
  256. #ifndef I2S_EXTERNAL_CLOCK_VAL
  257. uint32_t pllm = 0, plln = 0, pllr = 0;
  258. #endif /* I2S_EXTERNAL_CLOCK_VAL */
  259. /* Check the I2S parameters */
  260. assert_param(IS_SPI_23_PERIPH(SPIx));
  261. assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
  262. assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
  263. assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
  264. assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
  265. assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
  266. assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
  267. /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
  268. /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
  269. SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK;
  270. SPIx->I2SPR = 0x0002;
  271. /* Get the I2SCFGR register value */
  272. tmpreg = SPIx->I2SCFGR;
  273. /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
  274. if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
  275. {
  276. i2sodd = (uint16_t)0;
  277. i2sdiv = (uint16_t)2;
  278. }
  279. /* If the requested audio frequency is not the default, compute the prescaler */
  280. else
  281. {
  282. /* Check the frame length (For the Prescaler computing) *******************/
  283. if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
  284. {
  285. /* Packet length is 16 bits */
  286. packetlength = 1;
  287. }
  288. else
  289. {
  290. /* Packet length is 32 bits */
  291. packetlength = 2;
  292. }
  293. /* Get I2S source Clock frequency (only in Silicon RevisionB and RevisionY) */
  294. /* If an external I2S clock has to be used, this define should be set
  295. in the project configuration or in the stm32f2xx_conf.h file */
  296. #ifdef I2S_EXTERNAL_CLOCK_VAL
  297. /* Set external clock as I2S clock source */
  298. if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)
  299. {
  300. RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
  301. }
  302. /* Set the I2S clock to the external clock value */
  303. i2sclk = I2S_EXTERNAL_CLOCK_VAL;
  304. #else /* There is no define for External I2S clock source */
  305. /* Set PLLI2S as I2S clock source */
  306. if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)
  307. {
  308. RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
  309. }
  310. /* Get the PLLI2SN value */
  311. plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \
  312. (RCC_PLLI2SCFGR_PLLI2SN >> 6));
  313. /* Get the PLLI2SR value */
  314. pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \
  315. (RCC_PLLI2SCFGR_PLLI2SR >> 28));
  316. /* Get the PLLM value */
  317. pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
  318. /* Get the I2S source clock value */
  319. i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr);
  320. #endif /* I2S_EXTERNAL_CLOCK_VAL */
  321. /* Compute the Real divider depending on the MCLK output state, with a floating point */
  322. if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
  323. {
  324. /* MCLK output is enabled */
  325. tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
  326. }
  327. else
  328. {
  329. /* MCLK output is disabled */
  330. tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
  331. }
  332. /* Remove the flatting point */
  333. tmp = tmp / 10;
  334. /* Check the parity of the divider */
  335. i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
  336. /* Compute the i2sdiv prescaler */
  337. i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
  338. /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
  339. i2sodd = (uint16_t) (i2sodd << 8);
  340. }
  341. /* Test if the divider is 1 or 0 or greater than 0xFF */
  342. if ((i2sdiv < 2) || (i2sdiv > 0xFF))
  343. {
  344. /* Set the default values */
  345. i2sdiv = 2;
  346. i2sodd = 0;
  347. }
  348. /* Write to SPIx I2SPR register the computed value */
  349. SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
  350. /* Configure the I2S with the SPI_InitStruct values */
  351. tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
  352. (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
  353. (uint16_t)I2S_InitStruct->I2S_CPOL))));
  354. /* Write to SPIx I2SCFGR */
  355. SPIx->I2SCFGR = tmpreg;
  356. }
  357. /**
  358. * @brief Fills each SPI_InitStruct member with its default value.
  359. * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
  360. * @retval None
  361. */
  362. void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
  363. {
  364. /*--------------- Reset SPI init structure parameters values -----------------*/
  365. /* Initialize the SPI_Direction member */
  366. SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
  367. /* initialize the SPI_Mode member */
  368. SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
  369. /* initialize the SPI_DataSize member */
  370. SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
  371. /* Initialize the SPI_CPOL member */
  372. SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
  373. /* Initialize the SPI_CPHA member */
  374. SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
  375. /* Initialize the SPI_NSS member */
  376. SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
  377. /* Initialize the SPI_BaudRatePrescaler member */
  378. SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
  379. /* Initialize the SPI_FirstBit member */
  380. SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
  381. /* Initialize the SPI_CRCPolynomial member */
  382. SPI_InitStruct->SPI_CRCPolynomial = 7;
  383. }
  384. /**
  385. * @brief Fills each I2S_InitStruct member with its default value.
  386. * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.
  387. * @retval None
  388. */
  389. void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
  390. {
  391. /*--------------- Reset I2S init structure parameters values -----------------*/
  392. /* Initialize the I2S_Mode member */
  393. I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
  394. /* Initialize the I2S_Standard member */
  395. I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
  396. /* Initialize the I2S_DataFormat member */
  397. I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
  398. /* Initialize the I2S_MCLKOutput member */
  399. I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
  400. /* Initialize the I2S_AudioFreq member */
  401. I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
  402. /* Initialize the I2S_CPOL member */
  403. I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
  404. }
  405. /**
  406. * @brief Enables or disables the specified SPI peripheral.
  407. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
  408. * @param NewState: new state of the SPIx peripheral.
  409. * This parameter can be: ENABLE or DISABLE.
  410. * @retval None
  411. */
  412. void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
  413. {
  414. /* Check the parameters */
  415. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  416. assert_param(IS_FUNCTIONAL_STATE(NewState));
  417. if (NewState != DISABLE)
  418. {
  419. /* Enable the selected SPI peripheral */
  420. SPIx->CR1 |= SPI_CR1_SPE;
  421. }
  422. else
  423. {
  424. /* Disable the selected SPI peripheral */
  425. SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
  426. }
  427. }
  428. /**
  429. * @brief Enables or disables the specified SPI peripheral (in I2S mode).
  430. * @param SPIx: where x can be 2 or 3 to select the SPI peripheral.
  431. * @param NewState: new state of the SPIx peripheral.
  432. * This parameter can be: ENABLE or DISABLE.
  433. * @retval None
  434. */
  435. void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
  436. {
  437. /* Check the parameters */
  438. assert_param(IS_SPI_23_PERIPH(SPIx));
  439. assert_param(IS_FUNCTIONAL_STATE(NewState));
  440. if (NewState != DISABLE)
  441. {
  442. /* Enable the selected SPI peripheral (in I2S mode) */
  443. SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
  444. }
  445. else
  446. {
  447. /* Disable the selected SPI peripheral in I2S mode */
  448. SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
  449. }
  450. }
  451. /**
  452. * @brief Configures the data size for the selected SPI.
  453. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
  454. * @param SPI_DataSize: specifies the SPI data size.
  455. * This parameter can be one of the following values:
  456. * @arg SPI_DataSize_16b: Set data frame format to 16bit
  457. * @arg SPI_DataSize_8b: Set data frame format to 8bit
  458. * @retval None
  459. */
  460. void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
  461. {
  462. /* Check the parameters */
  463. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  464. assert_param(IS_SPI_DATASIZE(SPI_DataSize));
  465. /* Clear DFF bit */
  466. SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
  467. /* Set new DFF bit value */
  468. SPIx->CR1 |= SPI_DataSize;
  469. }
  470. /**
  471. * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.
  472. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
  473. * @param SPI_Direction: specifies the data transfer direction in bidirectional mode.
  474. * This parameter can be one of the following values:
  475. * @arg SPI_Direction_Tx: Selects Tx transmission direction
  476. * @arg SPI_Direction_Rx: Selects Rx receive direction
  477. * @retval None
  478. */
  479. void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
  480. {
  481. /* Check the parameters */
  482. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  483. assert_param(IS_SPI_DIRECTION(SPI_Direction));
  484. if (SPI_Direction == SPI_Direction_Tx)
  485. {
  486. /* Set the Tx only mode */
  487. SPIx->CR1 |= SPI_Direction_Tx;
  488. }
  489. else
  490. {
  491. /* Set the Rx only mode */
  492. SPIx->CR1 &= SPI_Direction_Rx;
  493. }
  494. }
  495. /**
  496. * @brief Configures internally by software the NSS pin for the selected SPI.
  497. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
  498. * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
  499. * This parameter can be one of the following values:
  500. * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
  501. * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
  502. * @retval None
  503. */
  504. void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
  505. {
  506. /* Check the parameters */
  507. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  508. assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
  509. if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
  510. {
  511. /* Set NSS pin internally by software */
  512. SPIx->CR1 |= SPI_NSSInternalSoft_Set;
  513. }
  514. else
  515. {
  516. /* Reset NSS pin internally by software */
  517. SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
  518. }
  519. }
  520. /**
  521. * @brief Enables or disables the SS output for the selected SPI.
  522. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
  523. * @param NewState: new state of the SPIx SS output.
  524. * This parameter can be: ENABLE or DISABLE.
  525. * @retval None
  526. */
  527. void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
  528. {
  529. /* Check the parameters */
  530. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  531. assert_param(IS_FUNCTIONAL_STATE(NewState));
  532. if (NewState != DISABLE)
  533. {
  534. /* Enable the selected SPI SS output */
  535. SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
  536. }
  537. else
  538. {
  539. /* Disable the selected SPI SS output */
  540. SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
  541. }
  542. }
  543. /**
  544. * @brief Enables or disables the SPIx/I2Sx DMA interface.
  545. *
  546. * @note This function can be called only after the SPI_Init() function has
  547. * been called.
  548. * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA
  549. * are not taken into consideration and are configured by hardware
  550. * respectively to the TI mode requirements.
  551. *
  552. * @param SPIx: where x can be 1, 2 or 3
  553. * @param NewState: new state of the selected SPI TI communication mode.
  554. * This parameter can be: ENABLE or DISABLE.
  555. * @retval None
  556. */
  557. void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
  558. {
  559. /* Check the parameters */
  560. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  561. assert_param(IS_FUNCTIONAL_STATE(NewState));
  562. if (NewState != DISABLE)
  563. {
  564. /* Enable the TI mode for the selected SPI peripheral */
  565. SPIx->CR2 |= SPI_CR2_FRF;
  566. }
  567. else
  568. {
  569. /* Disable the TI mode for the selected SPI peripheral */
  570. SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF;
  571. }
  572. }
  573. /**
  574. * @}
  575. */
  576. /** @defgroup SPI_Group2 Data transfers functions
  577. * @brief Data transfers functions
  578. *
  579. @verbatim
  580. ===============================================================================
  581. Data transfers functions
  582. ===============================================================================
  583. This section provides a set of functions allowing to manage the SPI data transfers
  584. In reception, data are received and then stored into an internal Rx buffer while
  585. In transmission, data are first stored into an internal Tx buffer before being
  586. transmitted.
  587. The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()
  588. function and returns the Rx buffered value. Whereas a write access to the SPI_DR
  589. can be done using SPI_I2S_SendData() function and stores the written data into
  590. Tx buffer.
  591. @endverbatim
  592. * @{
  593. */
  594. /**
  595. * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
  596. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
  597. * in SPI mode or 2 or 3 in I2S mode.
  598. * @retval The value of the received data.
  599. */
  600. uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
  601. {
  602. /* Check the parameters */
  603. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  604. /* Return the data in the DR register */
  605. return SPIx->DR;
  606. }
  607. /**
  608. * @brief Transmits a Data through the SPIx/I2Sx peripheral.
  609. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
  610. * in SPI mode or 2 or 3 in I2S mode.
  611. * @param Data: Data to be transmitted.
  612. * @retval None
  613. */
  614. void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
  615. {
  616. /* Check the parameters */
  617. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  618. /* Write in the DR register the data to be sent */
  619. SPIx->DR = Data;
  620. }
  621. /**
  622. * @}
  623. */
  624. /** @defgroup SPI_Group3 Hardware CRC Calculation functions
  625. * @brief Hardware CRC Calculation functions
  626. *
  627. @verbatim
  628. ===============================================================================
  629. Hardware CRC Calculation functions
  630. ===============================================================================
  631. This section provides a set of functions allowing to manage the SPI CRC hardware
  632. calculation
  633. SPI communication using CRC is possible through the following procedure:
  634. 1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,
  635. Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
  636. function.
  637. 2. Enable the CRC calculation using the SPI_CalculateCRC() function.
  638. 3. Enable the SPI using the SPI_Cmd() function
  639. 4. Before writing the last data to the TX buffer, set the CRCNext bit using the
  640. SPI_TransmitCRC() function to indicate that after transmission of the last
  641. data, the CRC should be transmitted.
  642. 5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
  643. bit is reset. The CRC is also received and compared against the SPI_RXCRCR
  644. value.
  645. If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
  646. can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
  647. @note It is advised not to read the calculated CRC values during the communication.
  648. @note When the SPI is in slave mode, be careful to enable CRC calculation only
  649. when the clock is stable, that is, when the clock is in the steady state.
  650. If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive
  651. to the SCK slave input clock as soon as CRCEN is set, and this, whatever
  652. the value of the SPE bit.
  653. @note With high bitrate frequencies, be careful when transmitting the CRC.
  654. As the number of used CPU cycles has to be as low as possible in the CRC
  655. transfer phase, it is forbidden to call software functions in the CRC
  656. transmission sequence to avoid errors in the last data and CRC reception.
  657. In fact, CRCNEXT bit has to be written before the end of the transmission/reception
  658. of the last data.
  659. @note For high bit rate frequencies, it is advised to use the DMA mode to avoid the
  660. degradation of the SPI speed performance due to CPU accesses impacting the
  661. SPI bandwidth.
  662. @note When the STM32F2xx is configured as slave and the NSS hardware mode is
  663. used, the NSS pin needs to be kept low between the data phase and the CRC
  664. phase.
  665. @note When the SPI is configured in slave mode with the CRC feature enabled, CRC
  666. calculation takes place even if a high level is applied on the NSS pin.
  667. This may happen for example in case of a multi-slave environment where the
  668. communication master addresses slaves alternately.
  669. @note Between a slave de-selection (high level on NSS) and a new slave selection
  670. (low level on NSS), the CRC value should be cleared on both master and slave
  671. sides in order to resynchronize the master and slave for their respective
  672. CRC calculation.
  673. @note To clear the CRC, follow the procedure below:
  674. 1. Disable SPI using the SPI_Cmd() function
  675. 2. Disable the CRC calculation using the SPI_CalculateCRC() function.
  676. 3. Enable the CRC calculation using the SPI_CalculateCRC() function.
  677. 4. Enable SPI using the SPI_Cmd() function.
  678. @endverbatim
  679. * @{
  680. */
  681. /**
  682. * @brief Enables or disables the CRC value calculation of the transferred bytes.
  683. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
  684. * @param NewState: new state of the SPIx CRC value calculation.
  685. * This parameter can be: ENABLE or DISABLE.
  686. * @retval None
  687. */
  688. void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
  689. {
  690. /* Check the parameters */
  691. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  692. assert_param(IS_FUNCTIONAL_STATE(NewState));
  693. if (NewState != DISABLE)
  694. {
  695. /* Enable the selected SPI CRC calculation */
  696. SPIx->CR1 |= SPI_CR1_CRCEN;
  697. }
  698. else
  699. {
  700. /* Disable the selected SPI CRC calculation */
  701. SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
  702. }
  703. }
  704. /**
  705. * @brief Transmit the SPIx CRC value.
  706. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
  707. * @retval None
  708. */
  709. void SPI_TransmitCRC(SPI_TypeDef* SPIx)
  710. {
  711. /* Check the parameters */
  712. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  713. /* Enable the selected SPI CRC transmission */
  714. SPIx->CR1 |= SPI_CR1_CRCNEXT;
  715. }
  716. /**
  717. * @brief Returns the transmit or the receive CRC register value for the specified SPI.
  718. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
  719. * @param SPI_CRC: specifies the CRC register to be read.
  720. * This parameter can be one of the following values:
  721. * @arg SPI_CRC_Tx: Selects Tx CRC register
  722. * @arg SPI_CRC_Rx: Selects Rx CRC register
  723. * @retval The selected CRC register value..
  724. */
  725. uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
  726. {
  727. uint16_t crcreg = 0;
  728. /* Check the parameters */
  729. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  730. assert_param(IS_SPI_CRC(SPI_CRC));
  731. if (SPI_CRC != SPI_CRC_Rx)
  732. {
  733. /* Get the Tx CRC register */
  734. crcreg = SPIx->TXCRCR;
  735. }
  736. else
  737. {
  738. /* Get the Rx CRC register */
  739. crcreg = SPIx->RXCRCR;
  740. }
  741. /* Return the selected CRC register */
  742. return crcreg;
  743. }
  744. /**
  745. * @brief Returns the CRC Polynomial register value for the specified SPI.
  746. * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
  747. * @retval The CRC Polynomial register value.
  748. */
  749. uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
  750. {
  751. /* Check the parameters */
  752. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  753. /* Return the CRC polynomial register */
  754. return SPIx->CRCPR;
  755. }
  756. /**
  757. * @}
  758. */
  759. /** @defgroup SPI_Group4 DMA transfers management functions
  760. * @brief DMA transfers management functions
  761. *
  762. @verbatim
  763. ===============================================================================
  764. DMA transfers management functions
  765. ===============================================================================
  766. @endverbatim
  767. * @{
  768. */
  769. /**
  770. * @brief Enables or disables the SPIx/I2Sx DMA interface.
  771. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
  772. * in SPI mode or 2 or 3 in I2S mode.
  773. * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled.
  774. * This parameter can be any combination of the following values:
  775. * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
  776. * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
  777. * @param NewState: new state of the selected SPI DMA transfer request.
  778. * This parameter can be: ENABLE or DISABLE.
  779. * @retval None
  780. */
  781. void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
  782. {
  783. /* Check the parameters */
  784. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  785. assert_param(IS_FUNCTIONAL_STATE(NewState));
  786. assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
  787. if (NewState != DISABLE)
  788. {
  789. /* Enable the selected SPI DMA requests */
  790. SPIx->CR2 |= SPI_I2S_DMAReq;
  791. }
  792. else
  793. {
  794. /* Disable the selected SPI DMA requests */
  795. SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
  796. }
  797. }
  798. /**
  799. * @}
  800. */
  801. /** @defgroup SPI_Group5 Interrupts and flags management functions
  802. * @brief Interrupts and flags management functions
  803. *
  804. @verbatim
  805. ===============================================================================
  806. Interrupts and flags management functions
  807. ===============================================================================
  808. This section provides a set of functions allowing to configure the SPI Interrupts
  809. sources and check or clear the flags or pending bits status.
  810. The user should identify which mode will be used in his application to manage
  811. the communication: Polling mode, Interrupt mode or DMA mode.
  812. Polling Mode
  813. =============
  814. In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
  815. 1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register
  816. 2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register
  817. 3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
  818. 4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur
  819. 5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur
  820. 6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur
  821. 7. I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs.
  822. 8. I2S_FLAG_UDR: to indicate an Underrun error occurs.
  823. 9. I2S_FLAG_CHSIDE: to indicate Channel Side.
  824. @note Do not use the BSY flag to handle each data transmission or reception. It is
  825. better to use the TXE and RXNE flags instead.
  826. In this Mode it is advised to use the following functions:
  827. - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
  828. - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
  829. Interrupt Mode
  830. ===============
  831. In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources
  832. and 7 pending bits:
  833. Pending Bits:
  834. -------------
  835. 1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register
  836. 2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register
  837. 3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only)
  838. 4. SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only)
  839. 5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur
  840. 6. I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only).
  841. 7. I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only).
  842. Interrupt Source:
  843. -----------------
  844. 1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty
  845. interrupt.
  846. 2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not
  847. empty interrupt.
  848. 3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
  849. In this Mode it is advised to use the following functions:
  850. - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
  851. - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
  852. - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
  853. DMA Mode
  854. ========
  855. In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
  856. 1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request
  857. 2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request
  858. In this Mode it is advised to use the following function:
  859. - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
  860. @endverbatim
  861. * @{
  862. */
  863. /**
  864. * @brief Enables or disables the specified SPI/I2S interrupts.
  865. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
  866. * in SPI mode or 2 or 3 in I2S mode.
  867. * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled.
  868. * This parameter can be one of the following values:
  869. * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
  870. * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
  871. * @arg SPI_I2S_IT_ERR: Error interrupt mask
  872. * @param NewState: new state of the specified SPI interrupt.
  873. * This parameter can be: ENABLE or DISABLE.
  874. * @retval None
  875. */
  876. void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
  877. {
  878. uint16_t itpos = 0, itmask = 0 ;
  879. /* Check the parameters */
  880. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  881. assert_param(IS_FUNCTIONAL_STATE(NewState));
  882. assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
  883. /* Get the SPI IT index */
  884. itpos = SPI_I2S_IT >> 4;
  885. /* Set the IT mask */
  886. itmask = (uint16_t)1 << (uint16_t)itpos;
  887. if (NewState != DISABLE)
  888. {
  889. /* Enable the selected SPI interrupt */
  890. SPIx->CR2 |= itmask;
  891. }
  892. else
  893. {
  894. /* Disable the selected SPI interrupt */
  895. SPIx->CR2 &= (uint16_t)~itmask;
  896. }
  897. }
  898. /**
  899. * @brief Checks whether the specified SPIx/I2Sx flag is set or not.
  900. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
  901. * in SPI mode or 2 or 3 in I2S mode.
  902. * @param SPI_I2S_FLAG: specifies the SPI flag to check.
  903. * This parameter can be one of the following values:
  904. * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
  905. * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
  906. * @arg SPI_I2S_FLAG_BSY: Busy flag.
  907. * @arg SPI_I2S_FLAG_OVR: Overrun flag.
  908. * @arg SPI_FLAG_MODF: Mode Fault flag.
  909. * @arg SPI_FLAG_CRCERR: CRC Error flag.
  910. * @arg SPI_I2S_FLAG_TIFRFE: Format Error.
  911. * @arg I2S_FLAG_UDR: Underrun Error flag.
  912. * @arg I2S_FLAG_CHSIDE: Channel Side flag.
  913. * @retval The new state of SPI_I2S_FLAG (SET or RESET).
  914. */
  915. FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
  916. {
  917. FlagStatus bitstatus = RESET;
  918. /* Check the parameters */
  919. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  920. assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
  921. /* Check the status of the specified SPI flag */
  922. if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
  923. {
  924. /* SPI_I2S_FLAG is set */
  925. bitstatus = SET;
  926. }
  927. else
  928. {
  929. /* SPI_I2S_FLAG is reset */
  930. bitstatus = RESET;
  931. }
  932. /* Return the SPI_I2S_FLAG status */
  933. return bitstatus;
  934. }
  935. /**
  936. * @brief Clears the SPIx CRC Error (CRCERR) flag.
  937. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
  938. * in SPI mode or 2 or 3 in I2S mode.
  939. * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
  940. * This function clears only CRCERR flag.
  941. * @arg SPI_FLAG_CRCERR: CRC Error flag.
  942. *
  943. * @note OVR (OverRun error) flag is cleared by software sequence: a read
  944. * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
  945. * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
  946. * @note UDR (UnderRun error) flag is cleared by a read operation to
  947. * SPI_SR register (SPI_I2S_GetFlagStatus()).
  948. * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write
  949. * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
  950. * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
  951. *
  952. * @retval None
  953. */
  954. void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
  955. {
  956. /* Check the parameters */
  957. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  958. assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
  959. /* Clear the selected SPI CRC Error (CRCERR) flag */
  960. SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
  961. }
  962. /**
  963. * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not.
  964. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
  965. * in SPI mode or 2 or 3 in I2S mode.
  966. * @param SPI_I2S_IT: specifies the SPI interrupt source to check.
  967. * This parameter can be one of the following values:
  968. * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
  969. * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
  970. * @arg SPI_I2S_IT_OVR: Overrun interrupt.
  971. * @arg SPI_IT_MODF: Mode Fault interrupt.
  972. * @arg SPI_IT_CRCERR: CRC Error interrupt.
  973. * @arg I2S_IT_UDR: Underrun interrupt.
  974. * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt.
  975. * @retval The new state of SPI_I2S_IT (SET or RESET).
  976. */
  977. ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
  978. {
  979. ITStatus bitstatus = RESET;
  980. uint16_t itpos = 0, itmask = 0, enablestatus = 0;
  981. /* Check the parameters */
  982. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  983. assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
  984. /* Get the SPI_I2S_IT index */
  985. itpos = 0x01 << (SPI_I2S_IT & 0x0F);
  986. /* Get the SPI_I2S_IT IT mask */
  987. itmask = SPI_I2S_IT >> 4;
  988. /* Set the IT mask */
  989. itmask = 0x01 << itmask;
  990. /* Get the SPI_I2S_IT enable bit status */
  991. enablestatus = (SPIx->CR2 & itmask) ;
  992. /* Check the status of the specified SPI interrupt */
  993. if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
  994. {
  995. /* SPI_I2S_IT is set */
  996. bitstatus = SET;
  997. }
  998. else
  999. {
  1000. /* SPI_I2S_IT is reset */
  1001. bitstatus = RESET;
  1002. }
  1003. /* Return the SPI_I2S_IT status */
  1004. return bitstatus;
  1005. }
  1006. /**
  1007. * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
  1008. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
  1009. * in SPI mode or 2 or 3 in I2S mode.
  1010. * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
  1011. * This function clears only CRCERR interrupt pending bit.
  1012. * @arg SPI_IT_CRCERR: CRC Error interrupt.
  1013. *
  1014. * @note OVR (OverRun Error) interrupt pending bit is cleared by software
  1015. * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
  1016. * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
  1017. * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read
  1018. * operation to SPI_SR register (SPI_I2S_GetITStatus()).
  1019. * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
  1020. * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
  1021. * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
  1022. * the SPI).
  1023. * @retval None
  1024. */
  1025. void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
  1026. {
  1027. uint16_t itpos = 0;
  1028. /* Check the parameters */
  1029. assert_param(IS_SPI_ALL_PERIPH(SPIx));
  1030. assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
  1031. /* Get the SPI_I2S IT index */
  1032. itpos = 0x01 << (SPI_I2S_IT & 0x0F);
  1033. /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
  1034. SPIx->SR = (uint16_t)~itpos;
  1035. }
  1036. /**
  1037. * @}
  1038. */
  1039. /**
  1040. * @}
  1041. */
  1042. /**
  1043. * @}
  1044. */
  1045. /**
  1046. * @}
  1047. */