core_cmFunc.h 16 KB

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  1. /**************************************************************************//**
  2. * @file core_cmFunc.h
  3. * @brief CMSIS Cortex-M Core Function Access Header File
  4. * @version V3.30
  5. * @date 17. February 2014
  6. *
  7. * @note
  8. *
  9. ******************************************************************************/
  10. /* Copyright (c) 2009 - 2014 ARM LIMITED
  11. All rights reserved.
  12. Redistribution and use in source and binary forms, with or without
  13. modification, are permitted provided that the following conditions are met:
  14. - Redistributions of source code must retain the above copyright
  15. notice, this list of conditions and the following disclaimer.
  16. - Redistributions in binary form must reproduce the above copyright
  17. notice, this list of conditions and the following disclaimer in the
  18. documentation and/or other materials provided with the distribution.
  19. - Neither the name of ARM nor the names of its contributors may be used
  20. to endorse or promote products derived from this software without
  21. specific prior written permission.
  22. *
  23. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  24. AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25. IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26. ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
  27. LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28. CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29. SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  30. INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  31. CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  32. ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  33. POSSIBILITY OF SUCH DAMAGE.
  34. ---------------------------------------------------------------------------*/
  35. #ifndef __CORE_CMFUNC_H
  36. #define __CORE_CMFUNC_H
  37. /* ########################### Core Function Access ########################### */
  38. /** \ingroup CMSIS_Core_FunctionInterface
  39. \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
  40. @{
  41. */
  42. #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
  43. /* ARM armcc specific functions */
  44. #if (__ARMCC_VERSION < 400677)
  45. #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
  46. #endif
  47. /* intrinsic void __enable_irq(); */
  48. /* intrinsic void __disable_irq(); */
  49. /** \brief Get Control Register
  50. This function returns the content of the Control Register.
  51. \return Control Register value
  52. */
  53. __STATIC_INLINE uint32_t __get_CONTROL(void)
  54. {
  55. register uint32_t __regControl __ASM("control");
  56. return(__regControl);
  57. }
  58. /** \brief Set Control Register
  59. This function writes the given value to the Control Register.
  60. \param [in] control Control Register value to set
  61. */
  62. __STATIC_INLINE void __set_CONTROL(uint32_t control)
  63. {
  64. register uint32_t __regControl __ASM("control");
  65. __regControl = control;
  66. }
  67. /** \brief Get IPSR Register
  68. This function returns the content of the IPSR Register.
  69. \return IPSR Register value
  70. */
  71. __STATIC_INLINE uint32_t __get_IPSR(void)
  72. {
  73. register uint32_t __regIPSR __ASM("ipsr");
  74. return(__regIPSR);
  75. }
  76. /** \brief Get APSR Register
  77. This function returns the content of the APSR Register.
  78. \return APSR Register value
  79. */
  80. __STATIC_INLINE uint32_t __get_APSR(void)
  81. {
  82. register uint32_t __regAPSR __ASM("apsr");
  83. return(__regAPSR);
  84. }
  85. /** \brief Get xPSR Register
  86. This function returns the content of the xPSR Register.
  87. \return xPSR Register value
  88. */
  89. __STATIC_INLINE uint32_t __get_xPSR(void)
  90. {
  91. register uint32_t __regXPSR __ASM("xpsr");
  92. return(__regXPSR);
  93. }
  94. /** \brief Get Process Stack Pointer
  95. This function returns the current value of the Process Stack Pointer (PSP).
  96. \return PSP Register value
  97. */
  98. __STATIC_INLINE uint32_t __get_PSP(void)
  99. {
  100. register uint32_t __regProcessStackPointer __ASM("psp");
  101. return(__regProcessStackPointer);
  102. }
  103. /** \brief Set Process Stack Pointer
  104. This function assigns the given value to the Process Stack Pointer (PSP).
  105. \param [in] topOfProcStack Process Stack Pointer value to set
  106. */
  107. __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
  108. {
  109. register uint32_t __regProcessStackPointer __ASM("psp");
  110. __regProcessStackPointer = topOfProcStack;
  111. }
  112. /** \brief Get Main Stack Pointer
  113. This function returns the current value of the Main Stack Pointer (MSP).
  114. \return MSP Register value
  115. */
  116. __STATIC_INLINE uint32_t __get_MSP(void)
  117. {
  118. register uint32_t __regMainStackPointer __ASM("msp");
  119. return(__regMainStackPointer);
  120. }
  121. /** \brief Set Main Stack Pointer
  122. This function assigns the given value to the Main Stack Pointer (MSP).
  123. \param [in] topOfMainStack Main Stack Pointer value to set
  124. */
  125. __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
  126. {
  127. register uint32_t __regMainStackPointer __ASM("msp");
  128. __regMainStackPointer = topOfMainStack;
  129. }
  130. /** \brief Get Priority Mask
  131. This function returns the current state of the priority mask bit from the Priority Mask Register.
  132. \return Priority Mask value
  133. */
  134. __STATIC_INLINE uint32_t __get_PRIMASK(void)
  135. {
  136. register uint32_t __regPriMask __ASM("primask");
  137. return(__regPriMask);
  138. }
  139. /** \brief Set Priority Mask
  140. This function assigns the given value to the Priority Mask Register.
  141. \param [in] priMask Priority Mask
  142. */
  143. __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
  144. {
  145. register uint32_t __regPriMask __ASM("primask");
  146. __regPriMask = (priMask);
  147. }
  148. #if (__CORTEX_M >= 0x03)
  149. /** \brief Enable FIQ
  150. This function enables FIQ interrupts by clearing the F-bit in the CPSR.
  151. Can only be executed in Privileged modes.
  152. */
  153. #define __enable_fault_irq __enable_fiq
  154. /** \brief Disable FIQ
  155. This function disables FIQ interrupts by setting the F-bit in the CPSR.
  156. Can only be executed in Privileged modes.
  157. */
  158. #define __disable_fault_irq __disable_fiq
  159. /** \brief Get Base Priority
  160. This function returns the current value of the Base Priority register.
  161. \return Base Priority register value
  162. */
  163. __STATIC_INLINE uint32_t __get_BASEPRI(void)
  164. {
  165. register uint32_t __regBasePri __ASM("basepri");
  166. return(__regBasePri);
  167. }
  168. /** \brief Set Base Priority
  169. This function assigns the given value to the Base Priority register.
  170. \param [in] basePri Base Priority value to set
  171. */
  172. __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
  173. {
  174. register uint32_t __regBasePri __ASM("basepri");
  175. __regBasePri = (basePri & 0xff);
  176. }
  177. /** \brief Get Fault Mask
  178. This function returns the current value of the Fault Mask register.
  179. \return Fault Mask register value
  180. */
  181. __STATIC_INLINE uint32_t __get_FAULTMASK(void)
  182. {
  183. register uint32_t __regFaultMask __ASM("faultmask");
  184. return(__regFaultMask);
  185. }
  186. /** \brief Set Fault Mask
  187. This function assigns the given value to the Fault Mask register.
  188. \param [in] faultMask Fault Mask value to set
  189. */
  190. __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
  191. {
  192. register uint32_t __regFaultMask __ASM("faultmask");
  193. __regFaultMask = (faultMask & (uint32_t)1);
  194. }
  195. #endif /* (__CORTEX_M >= 0x03) */
  196. #if (__CORTEX_M == 0x04)
  197. /** \brief Get FPSCR
  198. This function returns the current value of the Floating Point Status/Control register.
  199. \return Floating Point Status/Control register value
  200. */
  201. __STATIC_INLINE uint32_t __get_FPSCR(void)
  202. {
  203. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  204. register uint32_t __regfpscr __ASM("fpscr");
  205. return(__regfpscr);
  206. #else
  207. return(0);
  208. #endif
  209. }
  210. /** \brief Set FPSCR
  211. This function assigns the given value to the Floating Point Status/Control register.
  212. \param [in] fpscr Floating Point Status/Control value to set
  213. */
  214. __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
  215. {
  216. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  217. register uint32_t __regfpscr __ASM("fpscr");
  218. __regfpscr = (fpscr);
  219. #endif
  220. }
  221. #endif /* (__CORTEX_M == 0x04) */
  222. #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
  223. /* GNU gcc specific functions */
  224. /** \brief Enable IRQ Interrupts
  225. This function enables IRQ interrupts by clearing the I-bit in the CPSR.
  226. Can only be executed in Privileged modes.
  227. */
  228. __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
  229. {
  230. __ASM volatile ("cpsie i" : : : "memory");
  231. }
  232. /** \brief Disable IRQ Interrupts
  233. This function disables IRQ interrupts by setting the I-bit in the CPSR.
  234. Can only be executed in Privileged modes.
  235. */
  236. __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
  237. {
  238. __ASM volatile ("cpsid i" : : : "memory");
  239. }
  240. /** \brief Get Control Register
  241. This function returns the content of the Control Register.
  242. \return Control Register value
  243. */
  244. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
  245. {
  246. uint32_t result;
  247. __ASM volatile ("MRS %0, control" : "=r" (result) );
  248. return(result);
  249. }
  250. /** \brief Set Control Register
  251. This function writes the given value to the Control Register.
  252. \param [in] control Control Register value to set
  253. */
  254. __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
  255. {
  256. __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
  257. }
  258. /** \brief Get IPSR Register
  259. This function returns the content of the IPSR Register.
  260. \return IPSR Register value
  261. */
  262. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
  263. {
  264. uint32_t result;
  265. __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
  266. return(result);
  267. }
  268. /** \brief Get APSR Register
  269. This function returns the content of the APSR Register.
  270. \return APSR Register value
  271. */
  272. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
  273. {
  274. uint32_t result;
  275. __ASM volatile ("MRS %0, apsr" : "=r" (result) );
  276. return(result);
  277. }
  278. /** \brief Get xPSR Register
  279. This function returns the content of the xPSR Register.
  280. \return xPSR Register value
  281. */
  282. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
  283. {
  284. uint32_t result;
  285. __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
  286. return(result);
  287. }
  288. /** \brief Get Process Stack Pointer
  289. This function returns the current value of the Process Stack Pointer (PSP).
  290. \return PSP Register value
  291. */
  292. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
  293. {
  294. register uint32_t result;
  295. __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
  296. return(result);
  297. }
  298. /** \brief Set Process Stack Pointer
  299. This function assigns the given value to the Process Stack Pointer (PSP).
  300. \param [in] topOfProcStack Process Stack Pointer value to set
  301. */
  302. __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
  303. {
  304. __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
  305. }
  306. /** \brief Get Main Stack Pointer
  307. This function returns the current value of the Main Stack Pointer (MSP).
  308. \return MSP Register value
  309. */
  310. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
  311. {
  312. register uint32_t result;
  313. __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
  314. return(result);
  315. }
  316. /** \brief Set Main Stack Pointer
  317. This function assigns the given value to the Main Stack Pointer (MSP).
  318. \param [in] topOfMainStack Main Stack Pointer value to set
  319. */
  320. __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
  321. {
  322. __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
  323. }
  324. /** \brief Get Priority Mask
  325. This function returns the current state of the priority mask bit from the Priority Mask Register.
  326. \return Priority Mask value
  327. */
  328. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
  329. {
  330. uint32_t result;
  331. __ASM volatile ("MRS %0, primask" : "=r" (result) );
  332. return(result);
  333. }
  334. /** \brief Set Priority Mask
  335. This function assigns the given value to the Priority Mask Register.
  336. \param [in] priMask Priority Mask
  337. */
  338. __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
  339. {
  340. __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
  341. }
  342. #if (__CORTEX_M >= 0x03)
  343. /** \brief Enable FIQ
  344. This function enables FIQ interrupts by clearing the F-bit in the CPSR.
  345. Can only be executed in Privileged modes.
  346. */
  347. __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
  348. {
  349. __ASM volatile ("cpsie f" : : : "memory");
  350. }
  351. /** \brief Disable FIQ
  352. This function disables FIQ interrupts by setting the F-bit in the CPSR.
  353. Can only be executed in Privileged modes.
  354. */
  355. __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
  356. {
  357. __ASM volatile ("cpsid f" : : : "memory");
  358. }
  359. /** \brief Get Base Priority
  360. This function returns the current value of the Base Priority register.
  361. \return Base Priority register value
  362. */
  363. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
  364. {
  365. uint32_t result;
  366. __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
  367. return(result);
  368. }
  369. /** \brief Set Base Priority
  370. This function assigns the given value to the Base Priority register.
  371. \param [in] basePri Base Priority value to set
  372. */
  373. __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
  374. {
  375. __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
  376. }
  377. /** \brief Get Fault Mask
  378. This function returns the current value of the Fault Mask register.
  379. \return Fault Mask register value
  380. */
  381. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
  382. {
  383. uint32_t result;
  384. __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
  385. return(result);
  386. }
  387. /** \brief Set Fault Mask
  388. This function assigns the given value to the Fault Mask register.
  389. \param [in] faultMask Fault Mask value to set
  390. */
  391. __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
  392. {
  393. __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
  394. }
  395. #endif /* (__CORTEX_M >= 0x03) */
  396. #if (__CORTEX_M == 0x04)
  397. /** \brief Get FPSCR
  398. This function returns the current value of the Floating Point Status/Control register.
  399. \return Floating Point Status/Control register value
  400. */
  401. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
  402. {
  403. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  404. uint32_t result;
  405. /* Empty asm statement works as a scheduling barrier */
  406. __ASM volatile ("");
  407. __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
  408. __ASM volatile ("");
  409. return(result);
  410. #else
  411. return(0);
  412. #endif
  413. }
  414. /** \brief Set FPSCR
  415. This function assigns the given value to the Floating Point Status/Control register.
  416. \param [in] fpscr Floating Point Status/Control value to set
  417. */
  418. __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
  419. {
  420. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  421. /* Empty asm statement works as a scheduling barrier */
  422. __ASM volatile ("");
  423. __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
  424. __ASM volatile ("");
  425. #endif
  426. }
  427. #endif /* (__CORTEX_M == 0x04) */
  428. #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
  429. /* IAR iccarm specific functions */
  430. #include <cmsis_iar.h>
  431. #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
  432. /* TI CCS specific functions */
  433. #include <cmsis_ccs.h>
  434. #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
  435. /* TASKING carm specific functions */
  436. /*
  437. * The CMSIS functions have been implemented as intrinsics in the compiler.
  438. * Please use "carm -?i" to get an up to date list of all intrinsics,
  439. * Including the CMSIS ones.
  440. */
  441. #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
  442. /* Cosmic specific functions */
  443. #include <cmsis_csm.h>
  444. #endif
  445. /*@} end of CMSIS_Core_RegAccFunctions */
  446. #endif /* __CORE_CMFUNC_H */