startup_gd32f10x_md.s 14 KB

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  1. ;/*!
  2. ; \file startup_gd32f10x_md.s
  3. ; \brief start up file
  4. ;
  5. ; \version 2014-12-26, V1.0.0, firmware for GD32F10x
  6. ; \version 2017-06-20, V2.0.0, firmware for GD32F10x
  7. ; \version 2018-07-31, V2.1.0, firmware for GD32F10x
  8. ;*/
  9. ;
  10. ;/*
  11. ; Copyright (c) 2018, GigaDevice Semiconductor Inc.
  12. ;
  13. ; All rights reserved.
  14. ;
  15. ; Redistribution and use in source and binary forms, with or without modification,
  16. ;are permitted provided that the following conditions are met:
  17. ;
  18. ; 1. Redistributions of source code must retain the above copyright notice, this
  19. ; list of conditions and the following disclaimer.
  20. ; 2. Redistributions in binary form must reproduce the above copyright notice,
  21. ; this list of conditions and the following disclaimer in the documentation
  22. ; and/or other materials provided with the distribution.
  23. ; 3. Neither the name of the copyright holder nor the names of its contributors
  24. ; may be used to endorse or promote products derived from this software without
  25. ; specific prior written permission.
  26. ;
  27. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  28. ;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  29. ;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  30. ;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  31. ;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  32. ;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33. ;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  34. ;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  35. ;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  36. ;OF SUCH DAMAGE.
  37. ;*/
  38. ; <h> Stack Configuration
  39. ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
  40. ; </h>
  41. Stack_Size EQU 0x0001000
  42. AREA STACK, NOINIT, READWRITE, ALIGN = 3
  43. Stack_Mem SPACE Stack_Size
  44. __initial_sp
  45. ; <h> Heap Configuration
  46. ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
  47. ; </h>
  48. Heap_Size EQU 0x00002000
  49. AREA HEAP, NOINIT, READWRITE, ALIGN = 3
  50. __heap_base
  51. Heap_Mem SPACE Heap_Size
  52. __heap_limit
  53. PRESERVE8
  54. THUMB
  55. ; /* reset Vector Mapped to at Address 0 */
  56. AREA RESET, DATA, READONLY
  57. EXPORT __Vectors
  58. EXPORT __Vectors_End
  59. EXPORT __Vectors_Size
  60. __Vectors DCD __initial_sp ; Top of Stack
  61. DCD Reset_Handler ; Reset Handler
  62. DCD NMI_Handler ; NMI Handler
  63. DCD HardFault_Handler ; Hard Fault Handler
  64. DCD MemManage_Handler ; MPU Fault Handler
  65. DCD BusFault_Handler ; Bus Fault Handler
  66. DCD UsageFault_Handler ; Usage Fault Handler
  67. DCD 0 ; Reserved
  68. DCD 0 ; Reserved
  69. DCD 0 ; Reserved
  70. DCD 0 ; Reserved
  71. DCD SVC_Handler ; SVCall Handler
  72. DCD DebugMon_Handler ; Debug Monitor Handler
  73. DCD 0 ; Reserved
  74. DCD PendSV_Handler ; PendSV Handler
  75. DCD SysTick_Handler ; SysTick Handler
  76. ; /* external interrupts handler */
  77. DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
  78. DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
  79. DCD TAMPER_IRQHandler ; 18:Tamper Interrupt
  80. DCD RTC_IRQHandler ; 19:RTC through EXTI Line
  81. DCD FMC_IRQHandler ; 20:FMC
  82. DCD RCU_IRQHandler ; 21:RCU
  83. DCD EXTI0_IRQHandler ; 22:EXTI Line 0
  84. DCD EXTI1_IRQHandler ; 23:EXTI Line 1
  85. DCD EXTI2_IRQHandler ; 24:EXTI Line 2
  86. DCD EXTI3_IRQHandler ; 25:EXTI Line 3
  87. DCD EXTI4_IRQHandler ; 26:EXTI Line 4
  88. DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0
  89. DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1
  90. DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2
  91. DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3
  92. DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4
  93. DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5
  94. DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6
  95. DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
  96. DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX
  97. DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0
  98. DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
  99. DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
  100. DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9
  101. DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break
  102. DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update
  103. DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger
  104. DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
  105. DCD TIMER1_IRQHandler ; 44:TIMER1
  106. DCD TIMER2_IRQHandler ; 45:TIMER2
  107. DCD TIMER3_IRQHandler ; 46:TIMER3
  108. DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
  109. DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
  110. DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
  111. DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
  112. DCD SPI0_IRQHandler ; 51:SPI0
  113. DCD SPI1_IRQHandler ; 52:SPI1
  114. DCD USART0_IRQHandler ; 53:USART0
  115. DCD USART1_IRQHandler ; 54:USART1
  116. DCD USART2_IRQHandler ; 55:USART2
  117. DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15
  118. DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line
  119. DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line
  120. DCD 0 ; Reserved
  121. DCD 0 ; Reserved
  122. DCD 0 ; Reserved
  123. DCD 0 ; Reserved
  124. DCD 0 ; Reserved
  125. DCD EXMC_IRQHandler ; 64:EXMC
  126. __Vectors_End
  127. __Vectors_Size EQU __Vectors_End - __Vectors
  128. AREA |.text|, CODE, READONLY
  129. ;/* reset Handler */
  130. Reset_Handler PROC
  131. EXPORT Reset_Handler [WEAK]
  132. IMPORT __main
  133. IMPORT SystemInit
  134. LDR R0, =SystemInit
  135. BLX R0
  136. LDR R0, =__main
  137. BX R0
  138. ENDP
  139. ;/* dummy Exception Handlers */
  140. NMI_Handler PROC
  141. EXPORT NMI_Handler [WEAK]
  142. B .
  143. ENDP
  144. HardFault_Handler PROC
  145. EXPORT HardFault_Handler [WEAK]
  146. B .
  147. ENDP
  148. MemManage_Handler PROC
  149. EXPORT MemManage_Handler [WEAK]
  150. B .
  151. ENDP
  152. BusFault_Handler PROC
  153. EXPORT BusFault_Handler [WEAK]
  154. B .
  155. ENDP
  156. UsageFault_Handler PROC
  157. EXPORT UsageFault_Handler [WEAK]
  158. B .
  159. ENDP
  160. SVC_Handler PROC
  161. EXPORT SVC_Handler [WEAK]
  162. B .
  163. ENDP
  164. DebugMon_Handler PROC
  165. EXPORT DebugMon_Handler [WEAK]
  166. B .
  167. ENDP
  168. PendSV_Handler PROC
  169. EXPORT PendSV_Handler [WEAK]
  170. B .
  171. ENDP
  172. SysTick_Handler PROC
  173. EXPORT SysTick_Handler [WEAK]
  174. B .
  175. ENDP
  176. Default_Handler PROC
  177. ; /* external interrupts handler */
  178. EXPORT WWDGT_IRQHandler [WEAK]
  179. EXPORT LVD_IRQHandler [WEAK]
  180. EXPORT TAMPER_IRQHandler [WEAK]
  181. EXPORT RTC_IRQHandler [WEAK]
  182. EXPORT FMC_IRQHandler [WEAK]
  183. EXPORT RCU_IRQHandler [WEAK]
  184. EXPORT EXTI0_IRQHandler [WEAK]
  185. EXPORT EXTI1_IRQHandler [WEAK]
  186. EXPORT EXTI2_IRQHandler [WEAK]
  187. EXPORT EXTI3_IRQHandler [WEAK]
  188. EXPORT EXTI4_IRQHandler [WEAK]
  189. EXPORT DMA0_Channel0_IRQHandler [WEAK]
  190. EXPORT DMA0_Channel1_IRQHandler [WEAK]
  191. EXPORT DMA0_Channel2_IRQHandler [WEAK]
  192. EXPORT DMA0_Channel3_IRQHandler [WEAK]
  193. EXPORT DMA0_Channel4_IRQHandler [WEAK]
  194. EXPORT DMA0_Channel5_IRQHandler [WEAK]
  195. EXPORT DMA0_Channel6_IRQHandler [WEAK]
  196. EXPORT ADC0_1_IRQHandler [WEAK]
  197. EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK]
  198. EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK]
  199. EXPORT CAN0_RX1_IRQHandler [WEAK]
  200. EXPORT CAN0_EWMC_IRQHandler [WEAK]
  201. EXPORT EXTI5_9_IRQHandler [WEAK]
  202. EXPORT TIMER0_BRK_IRQHandler [WEAK]
  203. EXPORT TIMER0_UP_IRQHandler [WEAK]
  204. EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK]
  205. EXPORT TIMER0_Channel_IRQHandler [WEAK]
  206. EXPORT TIMER1_IRQHandler [WEAK]
  207. EXPORT TIMER2_IRQHandler [WEAK]
  208. EXPORT TIMER3_IRQHandler [WEAK]
  209. EXPORT I2C0_EV_IRQHandler [WEAK]
  210. EXPORT I2C0_ER_IRQHandler [WEAK]
  211. EXPORT I2C1_EV_IRQHandler [WEAK]
  212. EXPORT I2C1_ER_IRQHandler [WEAK]
  213. EXPORT SPI0_IRQHandler [WEAK]
  214. EXPORT SPI1_IRQHandler [WEAK]
  215. EXPORT USART0_IRQHandler [WEAK]
  216. EXPORT USART1_IRQHandler [WEAK]
  217. EXPORT USART2_IRQHandler [WEAK]
  218. EXPORT EXTI10_15_IRQHandler [WEAK]
  219. EXPORT RTC_Alarm_IRQHandler [WEAK]
  220. EXPORT USBD_WKUP_IRQHandler [WEAK]
  221. EXPORT EXMC_IRQHandler [WEAK]
  222. ;/* external interrupts handler */
  223. WWDGT_IRQHandler
  224. LVD_IRQHandler
  225. TAMPER_IRQHandler
  226. RTC_IRQHandler
  227. FMC_IRQHandler
  228. RCU_IRQHandler
  229. EXTI0_IRQHandler
  230. EXTI1_IRQHandler
  231. EXTI2_IRQHandler
  232. EXTI3_IRQHandler
  233. EXTI4_IRQHandler
  234. DMA0_Channel0_IRQHandler
  235. DMA0_Channel1_IRQHandler
  236. DMA0_Channel2_IRQHandler
  237. DMA0_Channel3_IRQHandler
  238. DMA0_Channel4_IRQHandler
  239. DMA0_Channel5_IRQHandler
  240. DMA0_Channel6_IRQHandler
  241. ADC0_1_IRQHandler
  242. USBD_HP_CAN0_TX_IRQHandler
  243. USBD_LP_CAN0_RX0_IRQHandler
  244. CAN0_RX1_IRQHandler
  245. CAN0_EWMC_IRQHandler
  246. EXTI5_9_IRQHandler
  247. TIMER0_BRK_IRQHandler
  248. TIMER0_UP_IRQHandler
  249. TIMER0_TRG_CMT_IRQHandler
  250. TIMER0_Channel_IRQHandler
  251. TIMER1_IRQHandler
  252. TIMER2_IRQHandler
  253. TIMER3_IRQHandler
  254. I2C0_EV_IRQHandler
  255. I2C0_ER_IRQHandler
  256. I2C1_EV_IRQHandler
  257. I2C1_ER_IRQHandler
  258. SPI0_IRQHandler
  259. SPI1_IRQHandler
  260. USART0_IRQHandler
  261. USART1_IRQHandler
  262. USART2_IRQHandler
  263. EXTI10_15_IRQHandler
  264. RTC_Alarm_IRQHandler
  265. USBD_WKUP_IRQHandler
  266. EXMC_IRQHandler
  267. B .
  268. ENDP
  269. ALIGN
  270. ; user Initial Stack & Heap
  271. IF :DEF:__MICROLIB
  272. EXPORT __initial_sp
  273. EXPORT __heap_base
  274. EXPORT __heap_limit
  275. ELSE
  276. IMPORT __use_two_region_memory
  277. EXPORT __user_initial_stackheap
  278. __user_initial_stackheap PROC
  279. LDR R0, = Heap_Mem
  280. LDR R1, =(Stack_Mem + Stack_Size)
  281. LDR R2, = (Heap_Mem + Heap_Size)
  282. LDR R3, = Stack_Mem
  283. BX LR
  284. ENDP
  285. ALIGN
  286. ENDIF
  287. END