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bootloader.htm

bootloader.htm 46 KB
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  1. <!doctype html public "-//w3c//dtd html 4.0 transitional//en">
    2. 

  2. <html><head>
    3. 

  3. <title>Static Call Graph - [..\OBJ\bootloader.axf]</title></head>
    4. 

  4. <body><HR>
    5. 

  5. <H1>Static Call Graph for image ..\OBJ\bootloader.axf</H1><HR>
    6. 

  6. <BR><P>#&#060CALLGRAPH&#062# ARM Linker, 5060750: Last Updated: Tue Aug 08 08:48:24 2023
    7. 

  7. <BR><P>
    8. 

  8. <H3>Maximum Stack Usage =       1088 bytes + Unknown(Cycles, Untraceable Function Pointers)</H3><H3>
    9. 

  9. Call chain for Maximum Stack Depth:</H3>
    10. 

  10. main &rArr; BootLoader_Brance &rArr; clear_ota_message_config_block &rArr; W25Q32_Erase64K &rArr; W25Q32_Enable &rArr; W25Q32_WaitBusy &rArr; SPI0_ReadWriteByte
    11. 

  11. <P>
    12. 

  12. <H3>
    13. 

  13. Mutually Recursive functions
    14. 

  14. </H3> <LI><a href="#[1c]">ADC0_1_IRQHandler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[1c]">ADC0_1_IRQHandler</a><BR>
    15. 

  15. </UL>
    16. 

  16. <P>
    17. 

  17. <H3>
    18. 

  18. Function Pointers
    19. 

  19. </H3><UL>
    20. 

  20.  <LI><a href="#[1c]">ADC0_1_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    21. 

  21.  <LI><a href="#[39]">ADC2_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    22. 

  22.  <LI><a href="#[4]">BusFault_Handler</a> from gd32f10x_it.o(i.BusFault_Handler) referenced from startup_gd32f10x_xd.o(RESET)
    23. 

  23.  <LI><a href="#[20]">CAN0_EWMC_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    24. 

  24.  <LI><a href="#[1f]">CAN0_RX1_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    25. 

  25.  <LI><a href="#[15]">DMA0_Channel0_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    26. 

  26.  <LI><a href="#[16]">DMA0_Channel1_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    27. 

  27.  <LI><a href="#[17]">DMA0_Channel2_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    28. 

  28.  <LI><a href="#[18]">DMA0_Channel3_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    29. 

  29.  <LI><a href="#[19]">DMA0_Channel4_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    30. 

  30.  <LI><a href="#[1a]">DMA0_Channel5_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    31. 

  31.  <LI><a href="#[1b]">DMA0_Channel6_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    32. 

  32.  <LI><a href="#[42]">DMA1_Channel0_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    33. 

  33.  <LI><a href="#[43]">DMA1_Channel1_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    34. 

  34.  <LI><a href="#[44]">DMA1_Channel2_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    35. 

  35.  <LI><a href="#[45]">DMA1_Channel3_4_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    36. 

  36.  <LI><a href="#[7]">DebugMon_Handler</a> from gd32f10x_it.o(i.DebugMon_Handler) referenced from startup_gd32f10x_xd.o(RESET)
    37. 

  37.  <LI><a href="#[3a]">EXMC_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    38. 

  38.  <LI><a href="#[10]">EXTI0_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    39. 

  39.  <LI><a href="#[32]">EXTI10_15_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    40. 

  40.  <LI><a href="#[11]">EXTI1_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    41. 

  41.  <LI><a href="#[12]">EXTI2_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    42. 

  42.  <LI><a href="#[13]">EXTI3_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    43. 

  43.  <LI><a href="#[14]">EXTI4_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    44. 

  44.  <LI><a href="#[21]">EXTI5_9_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    45. 

  45.  <LI><a href="#[e]">FMC_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    46. 

  46.  <LI><a href="#[2]">HardFault_Handler</a> from gd32f10x_it.o(i.HardFault_Handler) referenced from startup_gd32f10x_xd.o(RESET)
    47. 

  47.  <LI><a href="#[2a]">I2C0_ER_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    48. 

  48.  <LI><a href="#[29]">I2C0_EV_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    49. 

  49.  <LI><a href="#[2c]">I2C1_ER_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    50. 

  50.  <LI><a href="#[2b]">I2C1_EV_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    51. 

  51.  <LI><a href="#[b]">LVD_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    52. 

  52.  <LI><a href="#[3]">MemManage_Handler</a> from gd32f10x_it.o(i.MemManage_Handler) referenced from startup_gd32f10x_xd.o(RESET)
    53. 

  53.  <LI><a href="#[1]">NMI_Handler</a> from gd32f10x_it.o(i.NMI_Handler) referenced from startup_gd32f10x_xd.o(RESET)
    54. 

  54.  <LI><a href="#[8]">PendSV_Handler</a> from gd32f10x_it.o(i.PendSV_Handler) referenced from startup_gd32f10x_xd.o(RESET)
    55. 

  55.  <LI><a href="#[f]">RCU_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    56. 

  56.  <LI><a href="#[33]">RTC_Alarm_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    57. 

  57.  <LI><a href="#[d]">RTC_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    58. 

  58.  <LI><a href="#[0]">Reset_Handler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    59. 

  59.  <LI><a href="#[3b]">SDIO_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    60. 

  60.  <LI><a href="#[2d]">SPI0_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    61. 

  61.  <LI><a href="#[2e]">SPI1_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    62. 

  62.  <LI><a href="#[3d]">SPI2_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    63. 

  63.  <LI><a href="#[6]">SVC_Handler</a> from gd32f10x_it.o(i.SVC_Handler) referenced from startup_gd32f10x_xd.o(RESET)
    64. 

  64.  <LI><a href="#[9]">SysTick_Handler</a> from gd32f10x_it.o(i.SysTick_Handler) referenced from startup_gd32f10x_xd.o(RESET)
    65. 

  65.  <LI><a href="#[47]">SystemInit</a> from system_gd32f10x.o(i.SystemInit) referenced from startup_gd32f10x_xd.o(.text)
    66. 

  66.  <LI><a href="#[c]">TAMPER_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    67. 

  67.  <LI><a href="#[22]">TIMER0_BRK_TIMER8_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    68. 

  68.  <LI><a href="#[25]">TIMER0_Channel_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    69. 

  69.  <LI><a href="#[24]">TIMER0_TRG_CMT_TIMER10_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    70. 

  70.  <LI><a href="#[23]">TIMER0_UP_TIMER9_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    71. 

  71.  <LI><a href="#[26]">TIMER1_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    72. 

  72.  <LI><a href="#[27]">TIMER2_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    73. 

  73.  <LI><a href="#[28]">TIMER3_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    74. 

  74.  <LI><a href="#[3c]">TIMER4_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    75. 

  75.  <LI><a href="#[40]">TIMER5_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    76. 

  76.  <LI><a href="#[41]">TIMER6_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    77. 

  77.  <LI><a href="#[35]">TIMER7_BRK_TIMER11_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    78. 

  78.  <LI><a href="#[38]">TIMER7_Channel_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    79. 

  79.  <LI><a href="#[37]">TIMER7_TRG_CMT_TIMER13_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    80. 

  80.  <LI><a href="#[36]">TIMER7_UP_TIMER12_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    81. 

  81.  <LI><a href="#[3e]">UART3_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    82. 

  82.  <LI><a href="#[3f]">UART4_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    83. 

  83.  <LI><a href="#[2f]">USART0_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    84. 

  84.  <LI><a href="#[30]">USART1_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    85. 

  85.  <LI><a href="#[31]">USART2_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    86. 

  86.  <LI><a href="#[1d]">USBD_HP_CAN0_TX_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    87. 

  87.  <LI><a href="#[1e]">USBD_LP_CAN0_RX0_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    88. 

  88.  <LI><a href="#[34]">USBD_WKUP_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    89. 

  89.  <LI><a href="#[5]">UsageFault_Handler</a> from gd32f10x_it.o(i.UsageFault_Handler) referenced from startup_gd32f10x_xd.o(RESET)
    90. 

  90.  <LI><a href="#[a]">WWDGT_IRQHandler</a> from startup_gd32f10x_xd.o(.text) referenced from startup_gd32f10x_xd.o(RESET)
    91. 

  91.  <LI><a href="#[48]">__main</a> from entry.o(.ARM.Collect$$$$00000000) referenced from startup_gd32f10x_xd.o(.text)
    92. 

  92.  <LI><a href="#[46]">main</a> from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
    93. 

  93. </UL>
    94. 

  94. <P>
    95. 

  95. <H3>
    96. 

  96. Global Symbols
    97. 

  97. </H3>
    98. 

  98. <P><STRONG><a name="[48]"></a>__main</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
    99. 

  99. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(.text)
    100. 

  100. </UL>
    101. 

  101. <P><STRONG><a name="[7c]"></a>_main_stk</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
    102. 

  102. 

  103. <P><STRONG><a name="[49]"></a>_main_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
    104. 

  104. <BR><BR>[Calls]<UL><LI><a href="#[4a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
    105. 

  105. </UL>
    106. 

  106. 

  107. <P><STRONG><a name="[4e]"></a>__main_after_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
    108. 

  108. <BR><BR>[Called By]<UL><LI><a href="#[4a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
    109. 

  109. </UL>
    110. 

  110. 

  111. <P><STRONG><a name="[7d]"></a>_main_clock</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
    112. 

  112. 

  113. <P><STRONG><a name="[7e]"></a>_main_cpp_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
    114. 

  114. 

  115. <P><STRONG><a name="[7f]"></a>_main_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
    116. 

  116. 

  117. <P><STRONG><a name="[80]"></a>__rt_final_cpp</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D))
    118. 

  118. 

  119. <P><STRONG><a name="[81]"></a>__rt_final_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F))
    120. 

  120. 

  121. <P><STRONG><a name="[5e]"></a>MSR_SP</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, boot.o(.emb_text))
    122. 

  122. <BR><BR>[Called By]<UL><LI><a href="#[55]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;LOAD_A
    123. 

  123. </UL>
    124. 

  124. 

  125. <P><STRONG><a name="[0]"></a>Reset_Handler</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    126. 

  126. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    127. 

  127. </UL>
    128. 

  128. <P><STRONG><a name="[1c]"></a>ADC0_1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    129. 

  129. <BR><BR>[Calls]<UL><LI><a href="#[1c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC0_1_IRQHandler
    130. 

  130. </UL>
    131. 

  131. <BR>[Called By]<UL><LI><a href="#[1c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC0_1_IRQHandler
    132. 

  132. </UL>
    133. 

  133. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    134. 

  134. </UL>
    135. 

  135. <P><STRONG><a name="[39]"></a>ADC2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    136. 

  136. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    137. 

  137. </UL>
    138. 

  138. <P><STRONG><a name="[20]"></a>CAN0_EWMC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    139. 

  139. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    140. 

  140. </UL>
    141. 

  141. <P><STRONG><a name="[1f]"></a>CAN0_RX1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    142. 

  142. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    143. 

  143. </UL>
    144. 

  144. <P><STRONG><a name="[15]"></a>DMA0_Channel0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    145. 

  145. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    146. 

  146. </UL>
    147. 

  147. <P><STRONG><a name="[16]"></a>DMA0_Channel1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    148. 

  148. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    149. 

  149. </UL>
    150. 

  150. <P><STRONG><a name="[17]"></a>DMA0_Channel2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    151. 

  151. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    152. 

  152. </UL>
    153. 

  153. <P><STRONG><a name="[18]"></a>DMA0_Channel3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    154. 

  154. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    155. 

  155. </UL>
    156. 

  156. <P><STRONG><a name="[19]"></a>DMA0_Channel4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    157. 

  157. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    158. 

  158. </UL>
    159. 

  159. <P><STRONG><a name="[1a]"></a>DMA0_Channel5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    160. 

  160. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    161. 

  161. </UL>
    162. 

  162. <P><STRONG><a name="[1b]"></a>DMA0_Channel6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    163. 

  163. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    164. 

  164. </UL>
    165. 

  165. <P><STRONG><a name="[42]"></a>DMA1_Channel0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    166. 

  166. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    167. 

  167. </UL>
    168. 

  168. <P><STRONG><a name="[43]"></a>DMA1_Channel1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    169. 

  169. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    170. 

  170. </UL>
    171. 

  171. <P><STRONG><a name="[44]"></a>DMA1_Channel2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    172. 

  172. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    173. 

  173. </UL>
    174. 

  174. <P><STRONG><a name="[45]"></a>DMA1_Channel3_4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    175. 

  175. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    176. 

  176. </UL>
    177. 

  177. <P><STRONG><a name="[3a]"></a>EXMC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    178. 

  178. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    179. 

  179. </UL>
    180. 

  180. <P><STRONG><a name="[10]"></a>EXTI0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    181. 

  181. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    182. 

  182. </UL>
    183. 

  183. <P><STRONG><a name="[32]"></a>EXTI10_15_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    184. 

  184. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    185. 

  185. </UL>
    186. 

  186. <P><STRONG><a name="[11]"></a>EXTI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    187. 

  187. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    188. 

  188. </UL>
    189. 

  189. <P><STRONG><a name="[12]"></a>EXTI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    190. 

  190. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    191. 

  191. </UL>
    192. 

  192. <P><STRONG><a name="[13]"></a>EXTI3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    193. 

  193. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    194. 

  194. </UL>
    195. 

  195. <P><STRONG><a name="[14]"></a>EXTI4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    196. 

  196. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    197. 

  197. </UL>
    198. 

  198. <P><STRONG><a name="[21]"></a>EXTI5_9_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    199. 

  199. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    200. 

  200. </UL>
    201. 

  201. <P><STRONG><a name="[e]"></a>FMC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    202. 

  202. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    203. 

  203. </UL>
    204. 

  204. <P><STRONG><a name="[2a]"></a>I2C0_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    205. 

  205. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    206. 

  206. </UL>
    207. 

  207. <P><STRONG><a name="[29]"></a>I2C0_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    208. 

  208. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    209. 

  209. </UL>
    210. 

  210. <P><STRONG><a name="[2c]"></a>I2C1_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    211. 

  211. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    212. 

  212. </UL>
    213. 

  213. <P><STRONG><a name="[2b]"></a>I2C1_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    214. 

  214. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    215. 

  215. </UL>
    216. 

  216. <P><STRONG><a name="[b]"></a>LVD_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    217. 

  217. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    218. 

  218. </UL>
    219. 

  219. <P><STRONG><a name="[f]"></a>RCU_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    220. 

  220. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    221. 

  221. </UL>
    222. 

  222. <P><STRONG><a name="[33]"></a>RTC_Alarm_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    223. 

  223. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    224. 

  224. </UL>
    225. 

  225. <P><STRONG><a name="[d]"></a>RTC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    226. 

  226. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    227. 

  227. </UL>
    228. 

  228. <P><STRONG><a name="[3b]"></a>SDIO_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    229. 

  229. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    230. 

  230. </UL>
    231. 

  231. <P><STRONG><a name="[2d]"></a>SPI0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    232. 

  232. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    233. 

  233. </UL>
    234. 

  234. <P><STRONG><a name="[2e]"></a>SPI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    235. 

  235. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    236. 

  236. </UL>
    237. 

  237. <P><STRONG><a name="[3d]"></a>SPI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    238. 

  238. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    239. 

  239. </UL>
    240. 

  240. <P><STRONG><a name="[c]"></a>TAMPER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    241. 

  241. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    242. 

  242. </UL>
    243. 

  243. <P><STRONG><a name="[22]"></a>TIMER0_BRK_TIMER8_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    244. 

  244. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    245. 

  245. </UL>
    246. 

  246. <P><STRONG><a name="[25]"></a>TIMER0_Channel_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    247. 

  247. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    248. 

  248. </UL>
    249. 

  249. <P><STRONG><a name="[24]"></a>TIMER0_TRG_CMT_TIMER10_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    250. 

  250. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    251. 

  251. </UL>
    252. 

  252. <P><STRONG><a name="[23]"></a>TIMER0_UP_TIMER9_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    253. 

  253. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    254. 

  254. </UL>
    255. 

  255. <P><STRONG><a name="[26]"></a>TIMER1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    256. 

  256. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    257. 

  257. </UL>
    258. 

  258. <P><STRONG><a name="[27]"></a>TIMER2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    259. 

  259. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    260. 

  260. </UL>
    261. 

  261. <P><STRONG><a name="[28]"></a>TIMER3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    262. 

  262. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    263. 

  263. </UL>
    264. 

  264. <P><STRONG><a name="[3c]"></a>TIMER4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    265. 

  265. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    266. 

  266. </UL>
    267. 

  267. <P><STRONG><a name="[40]"></a>TIMER5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    268. 

  268. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    269. 

  269. </UL>
    270. 

  270. <P><STRONG><a name="[41]"></a>TIMER6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    271. 

  271. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    272. 

  272. </UL>
    273. 

  273. <P><STRONG><a name="[35]"></a>TIMER7_BRK_TIMER11_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    274. 

  274. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    275. 

  275. </UL>
    276. 

  276. <P><STRONG><a name="[38]"></a>TIMER7_Channel_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    277. 

  277. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    278. 

  278. </UL>
    279. 

  279. <P><STRONG><a name="[37]"></a>TIMER7_TRG_CMT_TIMER13_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    280. 

  280. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    281. 

  281. </UL>
    282. 

  282. <P><STRONG><a name="[36]"></a>TIMER7_UP_TIMER12_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    283. 

  283. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    284. 

  284. </UL>
    285. 

  285. <P><STRONG><a name="[3e]"></a>UART3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    286. 

  286. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    287. 

  287. </UL>
    288. 

  288. <P><STRONG><a name="[3f]"></a>UART4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    289. 

  289. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    290. 

  290. </UL>
    291. 

  291. <P><STRONG><a name="[2f]"></a>USART0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    292. 

  292. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    293. 

  293. </UL>
    294. 

  294. <P><STRONG><a name="[30]"></a>USART1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    295. 

  295. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    296. 

  296. </UL>
    297. 

  297. <P><STRONG><a name="[31]"></a>USART2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    298. 

  298. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    299. 

  299. </UL>
    300. 

  300. <P><STRONG><a name="[1d]"></a>USBD_HP_CAN0_TX_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    301. 

  301. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    302. 

  302. </UL>
    303. 

  303. <P><STRONG><a name="[1e]"></a>USBD_LP_CAN0_RX0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    304. 

  304. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    305. 

  305. </UL>
    306. 

  306. <P><STRONG><a name="[34]"></a>USBD_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    307. 

  307. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    308. 

  308. </UL>
    309. 

  309. <P><STRONG><a name="[a]"></a>WWDGT_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f10x_xd.o(.text))
    310. 

  310. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    311. 

  311. </UL>
    312. 

  312. <P><STRONG><a name="[4c]"></a>__aeabi_memset</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
    313. 

  313. <BR><BR>[Called By]<UL><LI><a href="#[4d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_memset$wrapper
    314. 

  314. <LI><a href="#[4b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr
    315. 

  315. </UL>
    316. 

  316. 

  317. <P><STRONG><a name="[82]"></a>__aeabi_memset4</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
    318. 

  318. 

  319. <P><STRONG><a name="[83]"></a>__aeabi_memset8</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
    320. 

  320. 

  321. <P><STRONG><a name="[4b]"></a>__aeabi_memclr</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
    322. 

  322. <BR><BR>[Calls]<UL><LI><a href="#[4c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memset
    323. 

  323. </UL>
    324. 

  324. 

  325. <P><STRONG><a name="[51]"></a>__aeabi_memclr4</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text))
    326. 

  326. <BR><BR>[Called By]<UL><LI><a href="#[4f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BootLoader_Brance
    327. 

  327. </UL>
    328. 

  328. 

  329. <P><STRONG><a name="[84]"></a>__aeabi_memclr8</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
    330. 

  330. 

  331. <P><STRONG><a name="[4d]"></a>_memset$wrapper</STRONG> (Thumb, 18 bytes, Stack size 8 bytes, memseta.o(.text), UNUSED)
    332. 

  332. <BR><BR>[Calls]<UL><LI><a href="#[4c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memset
    333. 

  333. </UL>
    334. 

  334. 

  335. <P><STRONG><a name="[4a]"></a>__scatterload</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
    336. 

  336. <BR><BR>[Calls]<UL><LI><a href="#[4e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__main_after_scatterload
    337. 

  337. </UL>
    338. 

  338. <BR>[Called By]<UL><LI><a href="#[49]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_main_scatterload
    339. 

  339. </UL>
    340. 

  340. 

  341. <P><STRONG><a name="[85]"></a>__scatterload_rt2</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
    342. 

  342. 

  343. <P><STRONG><a name="[4f]"></a>BootLoader_Brance</STRONG> (Thumb, 150 bytes, Stack size 1040 bytes, boot.o(i.BootLoader_Brance))
    344. 

  344. <BR><BR>[Stack]<UL><LI>Max Depth = 1088<LI>Call Chain = BootLoader_Brance &rArr; clear_ota_message_config_block &rArr; W25Q32_Erase64K &rArr; W25Q32_Enable &rArr; W25Q32_WaitBusy &rArr; SPI0_ReadWriteByte
    345. 

  345. </UL>
    346. 

  346. <BR>[Calls]<UL><LI><a href="#[54]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;clear_ota_message_config_block
    347. 

  347. <LI><a href="#[52]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Read
    348. 

  348. <LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GD32_WriteFlash
    349. 

  349. <LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GD32_EraseFlash
    350. 

  350. <LI><a href="#[55]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;LOAD_A
    351. 

  351. <LI><a href="#[51]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
    352. 

  352. </UL>
    353. 

  353. <BR>[Called By]<UL><LI><a href="#[46]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
    354. 

  354. </UL>
    355. 

  355. 

  356. <P><STRONG><a name="[56]"></a>BootLoader_Clear</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, boot.o(i.BootLoader_Clear))
    357. 

  357. <BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = BootLoader_Clear &rArr; gpio_deinit
    358. 

  358. </UL>
    359. 

  359. <BR>[Calls]<UL><LI><a href="#[57]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_deinit
    360. 

  360. </UL>
    361. 

  361. <BR>[Called By]<UL><LI><a href="#[55]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;LOAD_A
    362. 

  362. </UL>
    363. 

  363. 

  364. <P><STRONG><a name="[4]"></a>BusFault_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, gd32f10x_it.o(i.BusFault_Handler))
    365. 

  365. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    366. 

  366. </UL>
    367. 

  367. <P><STRONG><a name="[7]"></a>DebugMon_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, gd32f10x_it.o(i.DebugMon_Handler))
    368. 

  368. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    369. 

  369. </UL>
    370. 

  370. <P><STRONG><a name="[58]"></a>Delay_Init</STRONG> (Thumb, 10 bytes, Stack size 8 bytes, delay.o(i.Delay_Init))
    371. 

  371. <BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = Delay_Init
    372. 

  372. </UL>
    373. 

  373. <BR>[Calls]<UL><LI><a href="#[59]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;systick_clksource_set
    374. 

  374. </UL>
    375. 

  375. <BR>[Called By]<UL><LI><a href="#[46]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
    376. 

  376. </UL>
    377. 

  377. 

  378. <P><STRONG><a name="[50]"></a>GD32_EraseFlash</STRONG> (Thumb, 48 bytes, Stack size 16 bytes, fmc.o(i.GD32_EraseFlash))
    379. 

  379. <BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = GD32_EraseFlash &rArr; fmc_page_erase &rArr; fmc_bank1_ready_wait
    380. 

  380. </UL>
    381. 

  381. <BR>[Calls]<UL><LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_unlock
    382. 

  382. <LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_page_erase
    383. 

  383. <LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_lock
    384. 

  384. </UL>
    385. 

  385. <BR>[Called By]<UL><LI><a href="#[4f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BootLoader_Brance
    386. 

  386. </UL>
    387. 

  387. 

  388. <P><STRONG><a name="[53]"></a>GD32_WriteFlash</STRONG> (Thumb, 38 bytes, Stack size 16 bytes, fmc.o(i.GD32_WriteFlash))
    389. 

  389. <BR><BR>[Stack]<UL><LI>Max Depth = 36<LI>Call Chain = GD32_WriteFlash &rArr; fmc_word_program &rArr; fmc_bank1_ready_wait
    390. 

  390. </UL>
    391. 

  391. <BR>[Calls]<UL><LI><a href="#[5d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_word_program
    392. 

  392. <LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_unlock
    393. 

  393. <LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_lock
    394. 

  394. </UL>
    395. 

  395. <BR>[Called By]<UL><LI><a href="#[4f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BootLoader_Brance
    396. 

  396. </UL>
    397. 

  397. 

  398. <P><STRONG><a name="[2]"></a>HardFault_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, gd32f10x_it.o(i.HardFault_Handler))
    399. 

  399. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    400. 

  400. </UL>
    401. 

  401. <P><STRONG><a name="[55]"></a>LOAD_A</STRONG> (Thumb, 44 bytes, Stack size 8 bytes, boot.o(i.LOAD_A))
    402. 

  402. <BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = LOAD_A &rArr; BootLoader_Clear &rArr; gpio_deinit
    403. 

  403. </UL>
    404. 

  404. <BR>[Calls]<UL><LI><a href="#[56]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BootLoader_Clear
    405. 

  405. <LI><a href="#[5e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MSR_SP
    406. 

  406. </UL>
    407. 

  407. <BR>[Called By]<UL><LI><a href="#[4f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BootLoader_Brance
    408. 

  408. <LI><a href="#[46]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
    409. 

  409. </UL>
    410. 

  410. 

  411. <P><STRONG><a name="[3]"></a>MemManage_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, gd32f10x_it.o(i.MemManage_Handler))
    412. 

  412. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    413. 

  413. </UL>
    414. 

  414. <P><STRONG><a name="[1]"></a>NMI_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, gd32f10x_it.o(i.NMI_Handler))
    415. 

  415. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    416. 

  416. </UL>
    417. 

  417. <P><STRONG><a name="[8]"></a>PendSV_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, gd32f10x_it.o(i.PendSV_Handler))
    418. 

  418. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    419. 

  419. </UL>
    420. 

  420. <P><STRONG><a name="[5f]"></a>SPI0_Init</STRONG> (Thumb, 94 bytes, Stack size 32 bytes, spi.o(i.SPI0_Init))
    421. 

  421. <BR><BR>[Stack]<UL><LI>Max Depth = 52<LI>Call Chain = SPI0_Init &rArr; gpio_init
    422. 

  422. </UL>
    423. 

  423. <BR>[Calls]<UL><LI><a href="#[63]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;spi_init
    424. 

  424. <LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;spi_i2s_deinit
    425. 

  425. <LI><a href="#[64]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;spi_enable
    426. 

  426. <LI><a href="#[60]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;rcu_periph_clock_enable
    427. 

  427. <LI><a href="#[61]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_init
    428. 

  428. </UL>
    429. 

  429. <BR>[Called By]<UL><LI><a href="#[72]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Init
    430. 

  430. </UL>
    431. 

  431. 

  432. <P><STRONG><a name="[65]"></a>SPI0_Read</STRONG> (Thumb, 28 bytes, Stack size 16 bytes, spi.o(i.SPI0_Read))
    433. 

  433. <BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = SPI0_Read &rArr; SPI0_ReadWriteByte
    434. 

  434. </UL>
    435. 

  435. <BR>[Calls]<UL><LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_ReadWriteByte
    436. 

  436. </UL>
    437. 

  437. <BR>[Called By]<UL><LI><a href="#[52]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Read
    438. 

  438. </UL>
    439. 

  439. 

  440. <P><STRONG><a name="[66]"></a>SPI0_ReadWriteByte</STRONG> (Thumb, 50 bytes, Stack size 8 bytes, spi.o(i.SPI0_ReadWriteByte))
    441. 

  441. <BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = SPI0_ReadWriteByte
    442. 

  442. </UL>
    443. 

  443. <BR>[Calls]<UL><LI><a href="#[67]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;spi_i2s_flag_get
    444. 

  444. <LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;spi_i2s_data_transmit
    445. 

  445. <LI><a href="#[69]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;spi_i2s_data_receive
    446. 

  446. </UL>
    447. 

  447. <BR>[Called By]<UL><LI><a href="#[6e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_WaitBusy
    448. 

  448. <LI><a href="#[6d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Enable
    449. 

  449. <LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_Write
    450. 

  450. <LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_Read
    451. 

  451. </UL>
    452. 

  452. 

  453. <P><STRONG><a name="[6a]"></a>SPI0_Write</STRONG> (Thumb, 26 bytes, Stack size 16 bytes, spi.o(i.SPI0_Write))
    454. 

  454. <BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = SPI0_Write &rArr; SPI0_ReadWriteByte
    455. 

  455. </UL>
    456. 

  456. <BR>[Calls]<UL><LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_ReadWriteByte
    457. 

  457. </UL>
    458. 

  458. <BR>[Called By]<UL><LI><a href="#[71]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Erase64K
    459. 

  459. <LI><a href="#[52]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Read
    460. 

  460. </UL>
    461. 

  461. 

  462. <P><STRONG><a name="[6]"></a>SVC_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, gd32f10x_it.o(i.SVC_Handler))
    463. 

  463. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    464. 

  464. </UL>
    465. 

  465. <P><STRONG><a name="[9]"></a>SysTick_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, gd32f10x_it.o(i.SysTick_Handler))
    466. 

  466. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    467. 

  467. </UL>
    468. 

  468. <P><STRONG><a name="[47]"></a>SystemInit</STRONG> (Thumb, 196 bytes, Stack size 8 bytes, system_gd32f10x.o(i.SystemInit))
    469. 

  469. <BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = SystemInit &rArr; system_clock_config
    470. 

  470. </UL>
    471. 

  471. <BR>[Calls]<UL><LI><a href="#[6c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;nvic_vector_table_set
    472. 

  472. <LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_clock_config
    473. 

  473. </UL>
    474. 

  474. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(.text)
    475. 

  475. </UL>
    476. 

  476. <P><STRONG><a name="[5]"></a>UsageFault_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, gd32f10x_it.o(i.UsageFault_Handler))
    477. 

  477. <BR>[Address Reference Count : 1]<UL><LI> startup_gd32f10x_xd.o(RESET)
    478. 

  478. </UL>
    479. 

  479. <P><STRONG><a name="[6d]"></a>W25Q32_Enable</STRONG> (Thumb, 30 bytes, Stack size 8 bytes, w25q32.o(i.W25Q32_Enable))
    480. 

  480. <BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = W25Q32_Enable &rArr; W25Q32_WaitBusy &rArr; SPI0_ReadWriteByte
    481. 

  481. </UL>
    482. 

  482. <BR>[Calls]<UL><LI><a href="#[70]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_bit_set
    483. 

  483. <LI><a href="#[6f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_bit_reset
    484. 

  484. <LI><a href="#[6e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_WaitBusy
    485. 

  485. <LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_ReadWriteByte
    486. 

  486. </UL>
    487. 

  487. <BR>[Called By]<UL><LI><a href="#[71]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Erase64K
    488. 

  488. </UL>
    489. 

  489. 

  490. <P><STRONG><a name="[71]"></a>W25Q32_Erase64K</STRONG> (Thumb, 70 bytes, Stack size 16 bytes, w25q32.o(i.W25Q32_Erase64K))
    491. 

  491. <BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = W25Q32_Erase64K &rArr; W25Q32_Enable &rArr; W25Q32_WaitBusy &rArr; SPI0_ReadWriteByte
    492. 

  492. </UL>
    493. 

  493. <BR>[Calls]<UL><LI><a href="#[70]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_bit_set
    494. 

  494. <LI><a href="#[6f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_bit_reset
    495. 

  495. <LI><a href="#[6e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_WaitBusy
    496. 

  496. <LI><a href="#[6d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Enable
    497. 

  497. <LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_Write
    498. 

  498. </UL>
    499. 

  499. <BR>[Called By]<UL><LI><a href="#[54]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;clear_ota_message_config_block
    500. 

  500. </UL>
    501. 

  501. 

  502. <P><STRONG><a name="[72]"></a>W25Q32_Init</STRONG> (Thumb, 36 bytes, Stack size 8 bytes, w25q32.o(i.W25Q32_Init))
    503. 

  503. <BR><BR>[Stack]<UL><LI>Max Depth = 60<LI>Call Chain = W25Q32_Init &rArr; SPI0_Init &rArr; gpio_init
    504. 

  504. </UL>
    505. 

  505. <BR>[Calls]<UL><LI><a href="#[70]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_bit_set
    506. 

  506. <LI><a href="#[60]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;rcu_periph_clock_enable
    507. 

  507. <LI><a href="#[61]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_init
    508. 

  508. <LI><a href="#[5f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_Init
    509. 

  509. </UL>
    510. 

  510. <BR>[Called By]<UL><LI><a href="#[46]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
    511. 

  511. </UL>
    512. 

  512. 

  513. <P><STRONG><a name="[52]"></a>W25Q32_Read</STRONG> (Thumb, 70 bytes, Stack size 24 bytes, w25q32.o(i.W25Q32_Read))
    514. 

  514. <BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = W25Q32_Read &rArr; SPI0_Write &rArr; SPI0_ReadWriteByte
    515. 

  515. </UL>
    516. 

  516. <BR>[Calls]<UL><LI><a href="#[70]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_bit_set
    517. 

  517. <LI><a href="#[6f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_bit_reset
    518. 

  518. <LI><a href="#[6e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_WaitBusy
    519. 

  519. <LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_Write
    520. 

  520. <LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_Read
    521. 

  521. </UL>
    522. 

  522. <BR>[Called By]<UL><LI><a href="#[79]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;load_ota_message_config_params
    523. 

  523. <LI><a href="#[4f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BootLoader_Brance
    524. 

  524. </UL>
    525. 

  525. 

  526. <P><STRONG><a name="[6e]"></a>W25Q32_WaitBusy</STRONG> (Thumb, 44 bytes, Stack size 8 bytes, w25q32.o(i.W25Q32_WaitBusy))
    527. 

  527. <BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = W25Q32_WaitBusy &rArr; SPI0_ReadWriteByte
    528. 

  528. </UL>
    529. 

  529. <BR>[Calls]<UL><LI><a href="#[70]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_bit_set
    530. 

  530. <LI><a href="#[6f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_bit_reset
    531. 

  531. <LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_ReadWriteByte
    532. 

  532. </UL>
    533. 

  533. <BR>[Called By]<UL><LI><a href="#[71]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Erase64K
    534. 

  534. <LI><a href="#[6d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Enable
    535. 

  535. <LI><a href="#[52]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Read
    536. 

  536. </UL>
    537. 

  537. 

  538. <P><STRONG><a name="[86]"></a>__scatterload_copy</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
    539. 

  539. 

  540. <P><STRONG><a name="[87]"></a>__scatterload_null</STRONG> (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
    541. 

  541. 

  542. <P><STRONG><a name="[88]"></a>__scatterload_zeroinit</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
    543. 

  543. 

  544. <P><STRONG><a name="[54]"></a>clear_ota_message_config_block</STRONG> (Thumb, 10 bytes, Stack size 8 bytes, ota_message.o(i.clear_ota_message_config_block))
    545. 

  545. <BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = clear_ota_message_config_block &rArr; W25Q32_Erase64K &rArr; W25Q32_Enable &rArr; W25Q32_WaitBusy &rArr; SPI0_ReadWriteByte
    546. 

  546. </UL>
    547. 

  547. <BR>[Calls]<UL><LI><a href="#[71]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Erase64K
    548. 

  548. </UL>
    549. 

  549. <BR>[Called By]<UL><LI><a href="#[4f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BootLoader_Brance
    550. 

  550. </UL>
    551. 

  551. 

  552. <P><STRONG><a name="[73]"></a>fmc_bank0_ready_wait</STRONG> (Thumb, 34 bytes, Stack size 4 bytes, gd32f10x_fmc.o(i.fmc_bank0_ready_wait))
    553. 

  553. <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = fmc_bank0_ready_wait
    554. 

  554. </UL>
    555. 

  555. <BR>[Calls]<UL><LI><a href="#[74]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_bank0_state_get
    556. 

  556. </UL>
    557. 

  557. <BR>[Called By]<UL><LI><a href="#[5d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_word_program
    558. 

  558. <LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_page_erase
    559. 

  559. </UL>
    560. 

  560. 

  561. <P><STRONG><a name="[74]"></a>fmc_bank0_state_get</STRONG> (Thumb, 44 bytes, Stack size 0 bytes, gd32f10x_fmc.o(i.fmc_bank0_state_get))
    562. 

  562. <BR><BR>[Called By]<UL><LI><a href="#[73]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_bank0_ready_wait
    563. 

  563. </UL>
    564. 

  564. 

  565. <P><STRONG><a name="[75]"></a>fmc_bank1_ready_wait</STRONG> (Thumb, 34 bytes, Stack size 4 bytes, gd32f10x_fmc.o(i.fmc_bank1_ready_wait))
    566. 

  566. <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = fmc_bank1_ready_wait
    567. 

  567. </UL>
    568. 

  568. <BR>[Calls]<UL><LI><a href="#[76]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_bank1_state_get
    569. 

  569. </UL>
    570. 

  570. <BR>[Called By]<UL><LI><a href="#[5d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_word_program
    571. 

  571. <LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_page_erase
    572. 

  572. </UL>
    573. 

  573. 

  574. <P><STRONG><a name="[76]"></a>fmc_bank1_state_get</STRONG> (Thumb, 44 bytes, Stack size 0 bytes, gd32f10x_fmc.o(i.fmc_bank1_state_get))
    575. 

  575. <BR><BR>[Called By]<UL><LI><a href="#[75]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_bank1_ready_wait
    576. 

  576. </UL>
    577. 

  577. 

  578. <P><STRONG><a name="[5c]"></a>fmc_lock</STRONG> (Thumb, 34 bytes, Stack size 0 bytes, gd32f10x_fmc.o(i.fmc_lock))
    579. 

  579. <BR><BR>[Called By]<UL><LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GD32_WriteFlash
    580. 

  580. <LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GD32_EraseFlash
    581. 

  581. </UL>
    582. 

  582. 

  583. <P><STRONG><a name="[5b]"></a>fmc_page_erase</STRONG> (Thumb, 222 bytes, Stack size 12 bytes, gd32f10x_fmc.o(i.fmc_page_erase))
    584. 

  584. <BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = fmc_page_erase &rArr; fmc_bank1_ready_wait
    585. 

  585. </UL>
    586. 

  586. <BR>[Calls]<UL><LI><a href="#[75]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_bank1_ready_wait
    587. 

  587. <LI><a href="#[73]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_bank0_ready_wait
    588. 

  588. </UL>
    589. 

  589. <BR>[Called By]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GD32_EraseFlash
    590. 

  590. </UL>
    591. 

  591. 

  592. <P><STRONG><a name="[5a]"></a>fmc_unlock</STRONG> (Thumb, 52 bytes, Stack size 0 bytes, gd32f10x_fmc.o(i.fmc_unlock))
    593. 

  593. <BR><BR>[Called By]<UL><LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GD32_WriteFlash
    594. 

  594. <LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GD32_EraseFlash
    595. 

  595. </UL>
    596. 

  596. 

  597. <P><STRONG><a name="[5d]"></a>fmc_word_program</STRONG> (Thumb, 178 bytes, Stack size 16 bytes, gd32f10x_fmc.o(i.fmc_word_program))
    598. 

  598. <BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = fmc_word_program &rArr; fmc_bank1_ready_wait
    599. 

  599. </UL>
    600. 

  600. <BR>[Calls]<UL><LI><a href="#[75]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_bank1_ready_wait
    601. 

  601. <LI><a href="#[73]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fmc_bank0_ready_wait
    602. 

  602. </UL>
    603. 

  603. <BR>[Called By]<UL><LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GD32_WriteFlash
    604. 

  604. </UL>
    605. 

  605. 

  606. <P><STRONG><a name="[7a]"></a>get_config_params</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, ota_message.o(i.get_config_params))
    607. 

  607. <BR><BR>[Called By]<UL><LI><a href="#[46]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
    608. 

  608. </UL>
    609. 

  609. 

  610. <P><STRONG><a name="[6f]"></a>gpio_bit_reset</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, gd32f10x_gpio.o(i.gpio_bit_reset))
    611. 

  611. <BR><BR>[Called By]<UL><LI><a href="#[6e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_WaitBusy
    612. 

  612. <LI><a href="#[71]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Erase64K
    613. 

  613. <LI><a href="#[6d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Enable
    614. 

  614. <LI><a href="#[52]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Read
    615. 

  615. </UL>
    616. 

  616. 

  617. <P><STRONG><a name="[70]"></a>gpio_bit_set</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, gd32f10x_gpio.o(i.gpio_bit_set))
    618. 

  618. <BR><BR>[Called By]<UL><LI><a href="#[6e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_WaitBusy
    619. 

  619. <LI><a href="#[72]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Init
    620. 

  620. <LI><a href="#[71]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Erase64K
    621. 

  621. <LI><a href="#[6d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Enable
    622. 

  622. <LI><a href="#[52]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Read
    623. 

  623. </UL>
    624. 

  624. 

  625. <P><STRONG><a name="[57]"></a>gpio_deinit</STRONG> (Thumb, 186 bytes, Stack size 8 bytes, gd32f10x_gpio.o(i.gpio_deinit))
    626. 

  626. <BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = gpio_deinit
    627. 

  627. </UL>
    628. 

  628. <BR>[Calls]<UL><LI><a href="#[77]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;rcu_periph_reset_enable
    629. 

  629. <LI><a href="#[78]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;rcu_periph_reset_disable
    630. 

  630. </UL>
    631. 

  631. <BR>[Called By]<UL><LI><a href="#[56]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BootLoader_Clear
    632. 

  632. </UL>
    633. 

  633. 

  634. <P><STRONG><a name="[61]"></a>gpio_init</STRONG> (Thumb, 172 bytes, Stack size 20 bytes, gd32f10x_gpio.o(i.gpio_init))
    635. 

  635. <BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = gpio_init
    636. 

  636. </UL>
    637. 

  637. <BR>[Called By]<UL><LI><a href="#[72]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Init
    638. 

  638. <LI><a href="#[5f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_Init
    639. 

  639. </UL>
    640. 

  640. 

  641. <P><STRONG><a name="[79]"></a>load_ota_message_config_params</STRONG> (Thumb, 36 bytes, Stack size 8 bytes, ota_message.o(i.load_ota_message_config_params))
    642. 

  642. <BR><BR>[Stack]<UL><LI>Max Depth = 56<LI>Call Chain = load_ota_message_config_params &rArr; W25Q32_Read &rArr; SPI0_Write &rArr; SPI0_ReadWriteByte
    643. 

  643. </UL>
    644. 

  644. <BR>[Calls]<UL><LI><a href="#[52]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Read
    645. 

  645. </UL>
    646. 

  646. <BR>[Called By]<UL><LI><a href="#[46]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
    647. 

  647. </UL>
    648. 

  648. 

  649. <P><STRONG><a name="[46]"></a>main</STRONG> (Thumb, 38 bytes, Stack size 0 bytes, main.o(i.main))
    650. 

  650. <BR><BR>[Stack]<UL><LI>Max Depth = 1088<LI>Call Chain = main &rArr; BootLoader_Brance &rArr; clear_ota_message_config_block &rArr; W25Q32_Erase64K &rArr; W25Q32_Enable &rArr; W25Q32_WaitBusy &rArr; SPI0_ReadWriteByte
    651. 

  651. </UL>
    652. 

  652. <BR>[Calls]<UL><LI><a href="#[79]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;load_ota_message_config_params
    653. 

  653. <LI><a href="#[7a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;get_config_params
    654. 

  654. <LI><a href="#[72]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Init
    655. 

  655. <LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Delay_Init
    656. 

  656. <LI><a href="#[55]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;LOAD_A
    657. 

  657. <LI><a href="#[4f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BootLoader_Brance
    658. 

  658. </UL>
    659. 

  659. <BR>[Address Reference Count : 1]<UL><LI> entry9a.o(.ARM.Collect$$$$0000000B)
    660. 

  660. </UL>
    661. 

  661. <P><STRONG><a name="[6c]"></a>nvic_vector_table_set</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, gd32f10x_misc.o(i.nvic_vector_table_set))
    662. 

  662. <BR><BR>[Called By]<UL><LI><a href="#[47]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemInit
    663. 

  663. </UL>
    664. 

  664. 

  665. <P><STRONG><a name="[60]"></a>rcu_periph_clock_enable</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, gd32f10x_rcu.o(i.rcu_periph_clock_enable))
    666. 

  666. <BR><BR>[Called By]<UL><LI><a href="#[72]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;W25Q32_Init
    667. 

  667. <LI><a href="#[5f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_Init
    668. 

  668. </UL>
    669. 

  669. 

  670. <P><STRONG><a name="[78]"></a>rcu_periph_reset_disable</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, gd32f10x_rcu.o(i.rcu_periph_reset_disable))
    671. 

  671. <BR><BR>[Called By]<UL><LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;spi_i2s_deinit
    672. 

  672. <LI><a href="#[57]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_deinit
    673. 

  673. </UL>
    674. 

  674. 

  675. <P><STRONG><a name="[77]"></a>rcu_periph_reset_enable</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, gd32f10x_rcu.o(i.rcu_periph_reset_enable))
    676. 

  676. <BR><BR>[Called By]<UL><LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;spi_i2s_deinit
    677. 

  677. <LI><a href="#[57]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_deinit
    678. 

  678. </UL>
    679. 

  679. 

  680. <P><STRONG><a name="[64]"></a>spi_enable</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, gd32f10x_spi.o(i.spi_enable))
    681. 

  681. <BR><BR>[Called By]<UL><LI><a href="#[5f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_Init
    682. 

  682. </UL>
    683. 

  683. 

  684. <P><STRONG><a name="[69]"></a>spi_i2s_data_receive</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, gd32f10x_spi.o(i.spi_i2s_data_receive))
    685. 

  685. <BR><BR>[Called By]<UL><LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_ReadWriteByte
    686. 

  686. </UL>
    687. 

  687. 

  688. <P><STRONG><a name="[68]"></a>spi_i2s_data_transmit</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, gd32f10x_spi.o(i.spi_i2s_data_transmit))
    689. 

  689. <BR><BR>[Called By]<UL><LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_ReadWriteByte
    690. 

  690. </UL>
    691. 

  691. 

  692. <P><STRONG><a name="[62]"></a>spi_i2s_deinit</STRONG> (Thumb, 82 bytes, Stack size 8 bytes, gd32f10x_spi.o(i.spi_i2s_deinit))
    693. 

  693. <BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = spi_i2s_deinit
    694. 

  694. </UL>
    695. 

  695. <BR>[Calls]<UL><LI><a href="#[77]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;rcu_periph_reset_enable
    696. 

  696. <LI><a href="#[78]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;rcu_periph_reset_disable
    697. 

  697. </UL>
    698. 

  698. <BR>[Called By]<UL><LI><a href="#[5f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_Init
    699. 

  699. </UL>
    700. 

  700. 

  701. <P><STRONG><a name="[67]"></a>spi_i2s_flag_get</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, gd32f10x_spi.o(i.spi_i2s_flag_get))
    702. 

  702. <BR><BR>[Called By]<UL><LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_ReadWriteByte
    703. 

  703. </UL>
    704. 

  704. 

  705. <P><STRONG><a name="[63]"></a>spi_init</STRONG> (Thumb, 50 bytes, Stack size 0 bytes, gd32f10x_spi.o(i.spi_init))
    706. 

  706. <BR><BR>[Called By]<UL><LI><a href="#[5f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI0_Init
    707. 

  707. </UL>
    708. 

  708. 

  709. <P><STRONG><a name="[59]"></a>systick_clksource_set</STRONG> (Thumb, 40 bytes, Stack size 0 bytes, gd32f10x_misc.o(i.systick_clksource_set))
    710. 

  710. <BR><BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Delay_Init
    711. 

  711. </UL>
    712. 

  712. <P>
    713. 

  713. <H3>
    714. 

  714. Local Symbols
    715. 

  715. </H3>
    716. 

  716. <P><STRONG><a name="[7b]"></a>system_clock_108m_hxtal</STRONG> (Thumb, 182 bytes, Stack size 0 bytes, system_gd32f10x.o(i.system_clock_108m_hxtal))
    717. 

  717. <BR><BR>[Called By]<UL><LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_clock_config
    718. 

  718. </UL>
    719. 

  719. 

  720. <P><STRONG><a name="[6b]"></a>system_clock_config</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, system_gd32f10x.o(i.system_clock_config))
    721. 

  721. <BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = system_clock_config
    722. 

  722. </UL>
    723. 

  723. <BR>[Calls]<UL><LI><a href="#[7b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_clock_108m_hxtal
    724. 

  724. </UL>
    725. 

  725. <BR>[Called By]<UL><LI><a href="#[47]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemInit
    726. 

  726. </UL>
    727. 

  727. <P>
    728. 

  728. <H3>
    729. 

  729. Undefined Global Symbols
    730. 

  730. </H3><HR></body></html>
    731.