123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084 |
- #include "gd32f10x_enet.h"
- #ifdef GD32F10X_CL
- #if defined (__CC_ARM)
- __align(4)
- enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM];
- __align(4)
- enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM];
- __align(4)
- uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE];
- __align(4)
- uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE];
- #elif defined ( __ICCARM__ )
- #pragma data_alignment=4
- enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM];
- #pragma data_alignment=4
- enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM];
- #pragma data_alignment=4
- uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE];
- #pragma data_alignment=4
- uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE];
- #elif defined (__GNUC__)
- enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__ ((aligned (4)));
- enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__ ((aligned (4)));
- uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__ ((aligned (4)));
- uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__ ((aligned (4)));
- #endif
- enet_descriptors_struct *dma_current_txdesc;
- enet_descriptors_struct *dma_current_rxdesc;
- enet_descriptors_struct *dma_current_ptp_txdesc = NULL;
- enet_descriptors_struct *dma_current_ptp_rxdesc = NULL;
- static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
- static uint32_t enet_unknow_err = 0U;
- static const uint16_t enet_reg_tab[] = {
- 0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x1080, 0x001C, 0x0028, 0x002C,
- 0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C,
-
- 0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4,
-
- 0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720,
-
- 0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1048, 0x104C,
- 0x1050, 0x1054};
- void enet_deinit(void)
- {
- rcu_periph_reset_enable(RCU_ENETRST);
- rcu_periph_reset_disable(RCU_ENETRST);
- enet_initpara_reset();
- }
- void enet_initpara_config(enet_option_enum option, uint32_t para)
- {
- switch(option){
- case FORWARD_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION;
- enet_initpara.forward_frame = para;
- break;
- case DMABUS_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION;
- enet_initpara.dmabus_mode = para;
- break;
- case DMA_MAXBURST_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION;
- enet_initpara.dma_maxburst = para;
- break;
- case DMA_ARBITRATION_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION;
- enet_initpara.dma_arbitration = para;
- break;
- case STORE_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)STORE_OPTION;
- enet_initpara.store_forward_mode = para;
- break;
- case DMA_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)DMA_OPTION;
- enet_initpara.dma_function = para;
- break;
- case VLAN_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)VLAN_OPTION;
- enet_initpara.vlan_config = para;
- break;
- case FLOWCTL_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION;
- enet_initpara.flow_control = para;
- break;
- case HASHH_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)HASHH_OPTION;
- enet_initpara.hashtable_high = para;
- break;
- case HASHL_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)HASHL_OPTION;
- enet_initpara.hashtable_low = para;
- break;
- case FILTER_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)FILTER_OPTION;
- enet_initpara.framesfilter_mode = para;
- break;
- case HALFDUPLEX_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION;
- enet_initpara.halfduplex_param = para;
- break;
- case TIMER_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)TIMER_OPTION;
- enet_initpara.timer_config = para;
- break;
- case INTERFRAMEGAP_OPTION:
-
- enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION;
- enet_initpara.interframegap = para;
- break;
- default:
- break;
- }
- }
- ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept)
- {
- uint32_t reg_value=0U, reg_temp = 0U, temp = 0U;
- uint32_t media_temp = 0U;
- uint32_t timeout = 0U;
- uint16_t phy_value = 0U;
- ErrStatus phy_state= ERROR, enet_state = ERROR;
-
-
- if(ERROR == enet_phy_config()){
- _ENET_DELAY_(PHY_RESETDELAY);
- if(ERROR == enet_phy_config()){
- return enet_state;
- }
- }
-
- enet_default_init();
-
-
- media_temp = (uint32_t)mediamode;
-
- if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp){
-
- do{
- enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value);
- phy_value &= PHY_LINKED_STATUS;
- timeout++;
- }while((RESET == phy_value) && (timeout < PHY_READ_TO));
-
- if(PHY_READ_TO == timeout){
- return enet_state;
- }
-
- timeout = 0U;
-
-
- phy_value = PHY_AUTONEGOTIATION;
- phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value);
- if(!phy_state){
-
- return enet_state;
- }
-
-
- do{
- enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value);
- phy_value &= PHY_AUTONEGO_COMPLETE;
- timeout++;
- }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO));
-
- if(PHY_READ_TO == timeout){
- return enet_state;
- }
-
- timeout = 0U;
-
-
- enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value);
-
- if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){
- media_temp = ENET_MODE_FULLDUPLEX;
- }else{
- media_temp = ENET_MODE_HALFDUPLEX;
- }
-
- if((uint16_t)RESET !=(phy_value & PHY_SPEED_STATUS)){
- media_temp |= ENET_SPEEDMODE_10M;
- }else{
- media_temp |= ENET_SPEEDMODE_100M;
- }
- }else{
- phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3);
- phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1);
- phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value);
- if(!phy_state){
-
- return enet_state;
- }
-
- _ENET_DELAY_(PHY_CONFIGDELAY);
- }
-
- reg_value = ENET_MAC_CFG;
-
- reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM));
- reg_value |= media_temp;
- ENET_MAC_CFG = reg_value;
-
-
-
- if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){
- ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE;
-
- reg_value = ENET_DMA_CTL;
-
- reg_value &= ~ENET_DMA_CTL_DTCERFD;
- reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD);
- ENET_DMA_CTL = reg_value;
- }
-
-
- ENET_MAC_FRMF |= (uint32_t)recept;
-
-
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){
- reg_temp = enet_initpara.forward_frame;
-
- reg_value = ENET_MAC_CFG;
- temp = reg_temp;
-
- reg_value &= (~ENET_MAC_CFG_APCD);
- temp &= ENET_MAC_CFG_APCD;
- reg_value |= temp;
- ENET_MAC_CFG = reg_value;
-
- reg_value = ENET_DMA_CTL;
- temp = reg_temp;
-
- reg_value &= (~(ENET_DMA_CTL_FERF |ENET_DMA_CTL_FUF));
- temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF) << 2);
- reg_value |= (temp >> 2);
- ENET_DMA_CTL = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){
- temp = enet_initpara.dmabus_mode;
-
- reg_value = ENET_DMA_BCTL;
-
- reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \
- |ENET_DMA_BCTL_FPBL);
- reg_value |= temp;
- ENET_DMA_BCTL = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){
- temp = enet_initpara.dma_maxburst;
-
- reg_value = ENET_DMA_BCTL;
-
- reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP);
- reg_value |= temp;
- ENET_DMA_BCTL = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){
- temp = enet_initpara.dma_arbitration;
-
- reg_value = ENET_DMA_BCTL;
-
- reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB);
- reg_value |= temp;
- ENET_DMA_BCTL = reg_value;
- }
-
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){
- temp = enet_initpara.store_forward_mode;
-
- reg_value = ENET_DMA_CTL;
-
- reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC);
- reg_value |= temp;
- ENET_DMA_CTL = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){
- reg_temp = enet_initpara.dma_function;
-
- reg_value = ENET_DMA_CTL;
-
- reg_value &= (~(ENET_DMA_CTL_DAFRF |ENET_DMA_CTL_OSF));
- reg_value |= reg_temp;
- ENET_DMA_CTL = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){
- reg_temp = enet_initpara.vlan_config;
-
- reg_value = ENET_MAC_VLT;
-
- reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC);
- reg_value |= reg_temp;
- ENET_MAC_VLT = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){
- reg_temp = enet_initpara.flow_control;
-
- reg_value = ENET_MAC_FCTL;
- temp = reg_temp;
-
- reg_value &= ~(ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \
- | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN);
- temp &= (ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \
- | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN);
- reg_value |= temp;
- ENET_MAC_FCTL = reg_value;
-
- reg_value = ENET_MAC_FCTH;
- temp = reg_temp;
-
- reg_value &= ~(ENET_MAC_FCTH_RFA |ENET_MAC_FCTH_RFD);
- temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8);
- reg_value |= (temp >> 8);
- ENET_MAC_FCTH = reg_value;
- }
-
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){
- ENET_MAC_HLH = enet_initpara.hashtable_high;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){
- ENET_MAC_HLL = enet_initpara.hashtable_low;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){
- reg_temp = enet_initpara.framesfilter_mode;
-
- reg_value = ENET_MAC_FRMF;
-
- reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \
- | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \
- | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM);
- reg_value |= reg_temp;
- ENET_MAC_FRMF = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){
- reg_temp = enet_initpara.halfduplex_param;
-
- reg_value = ENET_MAC_CFG;
-
- reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \
- | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC);
- reg_value |= reg_temp;
- ENET_MAC_CFG = reg_value;
- }
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){
- reg_temp = enet_initpara.timer_config;
-
- reg_value = ENET_MAC_CFG;
-
- reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD);
- reg_value |= reg_temp;
- ENET_MAC_CFG = reg_value;
- }
-
-
- if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){
- reg_temp = enet_initpara.interframegap;
-
- reg_value = ENET_MAC_CFG;
-
- reg_value &= ~ENET_MAC_CFG_IGBS;
- reg_value |= reg_temp;
- ENET_MAC_CFG = reg_value;
- }
- enet_state = SUCCESS;
- return enet_state;
- }
- ErrStatus enet_software_reset(void)
- {
- uint32_t timeout = 0U;
- ErrStatus enet_state = ERROR;
- uint32_t dma_flag;
-
-
- ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR;
-
-
- do{
- dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR);
- timeout++;
- }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout));
-
- if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){
- enet_state = SUCCESS;
- }
-
- return enet_state;
- }
- uint32_t enet_rxframe_size_get(void)
- {
- uint32_t size = 0U;
- uint32_t status;
-
-
- status = dma_current_rxdesc->status;
-
-
- if((uint32_t)RESET != (status & ENET_RDES0_DAV)){
- return 0U;
- }
-
-
- if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) ||
- (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) ||
- (((uint32_t)RESET) == (status & ENET_RDES0_FDES))){
-
- enet_rxframe_drop();
- return 1U;
- }
-
- if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) &&
- (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){
-
- enet_rxframe_drop();
- return 1U;
- }
-
- if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) &&
- (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) &&
- (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) &&
- (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){
-
- size = GET_RDES0_FRML(status);
-
- size = size - 4U;
- }else{
- enet_unknow_err++;
- enet_rxframe_drop();
- return 1U;
- }
-
-
- return size;
- }
- void enet_descriptors_chain_init(enet_dmadirection_enum direction)
- {
- uint32_t num = 0U, count = 0U, maxsize = 0U;
- uint32_t desc_status = 0U, desc_bufsize = 0U;
- enet_descriptors_struct *desc, *desc_tab;
- uint8_t *buf;
-
- if (ENET_DMA_TX == direction){
-
- desc_tab = txdesc_tab;
- buf = &tx_buff[0][0];
- count = ENET_TXBUF_NUM;
- maxsize = ENET_TXBUF_SIZE;
-
-
- desc_status = ENET_TDES0_TCHM;
-
-
- ENET_DMA_TDTADDR = (uint32_t)desc_tab;
- dma_current_txdesc = desc_tab;
- }else{
-
-
- desc_tab = rxdesc_tab;
- buf = &rx_buff[0][0];
- count = ENET_RXBUF_NUM;
- maxsize = ENET_RXBUF_SIZE;
-
-
- desc_status = ENET_RDES0_DAV;
-
- desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE;
-
-
- ENET_DMA_RDTADDR = (uint32_t)desc_tab;
- dma_current_rxdesc = desc_tab;
- }
- dma_current_ptp_rxdesc = NULL;
- dma_current_ptp_txdesc = NULL;
-
-
- for(num=0U; num < count; num++){
-
- desc = desc_tab + num;
-
- desc->status = desc_status;
- desc->control_buffer_size = desc_bufsize;
- desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
-
-
- if(num < (count - 1U)){
-
- desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U);
- }else{
-
-
- desc->buffer2_next_desc_addr = (uint32_t) desc_tab;
- }
- }
- }
- void enet_descriptors_ring_init(enet_dmadirection_enum direction)
- {
- uint32_t num = 0U, count = 0U, maxsize = 0U;
- uint32_t desc_status = 0U, desc_bufsize = 0U;
- enet_descriptors_struct *desc;
- enet_descriptors_struct *desc_tab;
- uint8_t *buf;
-
-
- ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL;
- ENET_DMA_BCTL |= DMA_BCTL_DPSL(0);
-
-
- if (ENET_DMA_TX == direction){
-
- desc_tab = txdesc_tab;
- buf = &tx_buff[0][0];
- count = ENET_TXBUF_NUM;
- maxsize = ENET_TXBUF_SIZE;
-
-
- ENET_DMA_TDTADDR = (uint32_t)desc_tab;
- dma_current_txdesc = desc_tab;
- }else{
-
-
- desc_tab = rxdesc_tab;
- buf = &rx_buff[0][0];
- count = ENET_RXBUF_NUM;
- maxsize = ENET_RXBUF_SIZE;
-
-
- desc_status = ENET_RDES0_DAV;
-
- desc_bufsize = ENET_RXBUF_SIZE;
-
-
- ENET_DMA_RDTADDR = (uint32_t)desc_tab;
- dma_current_rxdesc = desc_tab;
- }
- dma_current_ptp_rxdesc = NULL;
- dma_current_ptp_txdesc = NULL;
-
-
- for(num=0U; num < count; num++){
-
- desc = desc_tab + num;
-
- desc->status = desc_status;
- desc->control_buffer_size = desc_bufsize;
- desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
-
-
- if(num == (count - 1U)){
- if (ENET_DMA_TX == direction){
-
- desc->status |= ENET_TDES0_TERM;
- }else{
-
- desc->control_buffer_size |= ENET_RDES1_RERM;
- }
- }
- }
- }
- ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize)
- {
- uint32_t offset = 0U, size = 0U;
-
-
- if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){
- return ERROR;
- }
-
-
- if(NULL != buffer){
-
- if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) &&
- (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) &&
- (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){
-
- size = GET_RDES0_FRML(dma_current_rxdesc->status);
- size = size - 4U;
-
-
- if(size > bufsize){
- return ERROR;
- }
-
-
- for(offset = 0U; offset<size; offset++){
- (*(buffer + offset)) = (*(__IO uint8_t *) (uint32_t)((dma_current_rxdesc->buffer1_addr) + offset));
- }
-
- }else{
-
- return ERROR;
- }
- }
-
- dma_current_rxdesc->status = ENET_RDES0_DAV;
-
-
- if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){
-
- ENET_DMA_STAT = ENET_DMA_STAT_RBU;
-
- ENET_DMA_RPEN = 0U;
- }
-
-
-
- if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
- dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr);
- }else{
-
- if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
-
- dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
- }else{
-
- dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)));
- }
- }
-
- return SUCCESS;
- }
- ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length)
- {
- uint32_t offset = 0U;
- uint32_t dma_tbu_flag, dma_tu_flag;
-
-
- if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){
- return ERROR;
- }
-
-
- if(length > ENET_MAX_FRAME_SIZE){
- return ERROR;
- }
-
-
- if(NULL != buffer){
-
- for(offset = 0U; offset < length; offset++){
- (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset));
- }
- }
-
-
- dma_current_txdesc->control_buffer_size = length;
-
- dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG;
-
- dma_current_txdesc->status |= ENET_TDES0_DAV;
-
-
- dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU);
- dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU);
-
- if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){
-
- ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag);
-
- ENET_DMA_TPEN = 0U;
- }
-
-
-
- if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){
- dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr);
- }else{
-
- if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){
-
- dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR);
- }else{
-
- dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)));
- }
- }
- return SUCCESS;
- }
- void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum)
- {
- desc->status &= ~ENET_TDES0_CM;
- desc->status |= checksum;
- }
- void enet_enable(void)
- {
- enet_tx_enable();
- enet_rx_enable();
- }
- void enet_disable(void)
- {
- enet_tx_disable();
- enet_rx_disable();
- }
-
- void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[])
- {
- REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr);
- REG32(ENET_ADDRL_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRL(paddr);
- }
-
- void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[])
- {
- paddr[0] = ENET_GET_MACADDR(mac_addr, 0U);
- paddr[1] = ENET_GET_MACADDR(mac_addr, 1U);
- paddr[2] = ENET_GET_MACADDR(mac_addr, 2U);
- paddr[3] = ENET_GET_MACADDR(mac_addr, 3U);
- paddr[4] = ENET_GET_MACADDR(mac_addr, 4U);
- paddr[5] = ENET_GET_MACADDR(mac_addr, 5U);
- }
- FlagStatus enet_flag_get(enet_flag_enum enet_flag)
- {
- if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))){
- return SET;
- }else{
- return RESET;
- }
- }
- void enet_flag_clear(enet_flag_clear_enum enet_flag)
- {
-
- ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag));
- }
- void enet_interrupt_enable(enet_int_enum enet_int)
- {
- if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){
-
- ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int));
- }else{
-
- ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int));
- }
- }
- void enet_interrupt_disable(enet_int_enum enet_int)
- {
- if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){
-
- ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int));
- }else{
-
- ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int));
- }
- }
- FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag)
- {
- if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))){
- return SET;
- }else{
- return RESET;
- }
- }
- void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear)
- {
-
- ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear));
- }
- void enet_tx_enable(void)
- {
- ENET_MAC_CFG |= ENET_MAC_CFG_TEN;
- enet_txfifo_flush();
- ENET_DMA_CTL |= ENET_DMA_CTL_STE;
- }
- void enet_tx_disable(void)
- {
- ENET_DMA_CTL &= ~ENET_DMA_CTL_STE;
- enet_txfifo_flush();
- ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN;
- }
- void enet_rx_enable(void)
- {
- ENET_MAC_CFG |= ENET_MAC_CFG_REN;
- ENET_DMA_CTL |= ENET_DMA_CTL_SRE;
- }
- void enet_rx_disable(void)
- {
- ENET_DMA_CTL &= ~ENET_DMA_CTL_SRE;
- ENET_MAC_CFG &= ~ENET_MAC_CFG_REN;
- }
- void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num)
- {
- uint32_t offset = 0U, max = 0U, limit = 0U;
-
- offset = (uint32_t)type;
- max = (uint32_t)type + num;
- limit = sizeof(enet_reg_tab)/sizeof(uint16_t);
-
-
- if(max > limit){
- max = limit;
- }
-
- for(; offset < max; offset++){
-
- *preg = REG32((ENET) + enet_reg_tab[offset]);
- preg++;
- }
- }
- void enet_address_filter_enable(enet_macaddress_enum mac_addr)
- {
- REG32(ENET_ADDRH_BASE + mac_addr) |= ENET_MAC_ADDR1H_AFE;
- }
- void enet_address_filter_disable(enet_macaddress_enum mac_addr)
- {
- REG32(ENET_ADDRH_BASE + mac_addr) &= ~ENET_MAC_ADDR1H_AFE;
- }
- void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type)
- {
- uint32_t reg;
-
-
- reg = REG32(ENET_ADDRH_BASE + mac_addr);
-
- reg &= ~(ENET_MAC_ADDR1H_MB | ENET_MAC_ADDR1H_SAF);
- reg |= (addr_mask | filter_type);
- REG32(ENET_ADDRH_BASE + mac_addr) = reg;
- }
-
- ErrStatus enet_phy_config(void)
- {
- uint32_t ahbclk;
- uint32_t reg;
- uint16_t phy_value;
- ErrStatus enet_state = ERROR;
-
-
- reg = ENET_MAC_PHY_CTL;
- reg &= ~ENET_MAC_PHY_CTL_CLR;
-
- ahbclk = rcu_clock_freq_get(CK_AHB);
-
-
- if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){
- reg |= ENET_MDC_HCLK_DIV16;
- }else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)){
- reg |= ENET_MDC_HCLK_DIV26;
- }else if(ENET_RANGE(ahbclk, 60000000U, 90000000U)){
- reg |= ENET_MDC_HCLK_DIV42;
- }else if((ENET_RANGE(ahbclk, 90000000U, 108000000U))||(108000000U == ahbclk)){
- reg |= ENET_MDC_HCLK_DIV62;
- }else{
- return enet_state;
- }
- ENET_MAC_PHY_CTL = reg;
-
- phy_value = PHY_RESET;
- if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){
- return enet_state;
- }
-
- _ENET_DELAY_(ENET_DELAY_TO);
-
-
- if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){
- return enet_state;
- }
-
- if(RESET == (phy_value & PHY_RESET)){
- enet_state = SUCCESS;
- }
-
- return enet_state;
- }
- ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue)
- {
- uint32_t reg, phy_flag;
- uint32_t timeout = 0U;
- ErrStatus enet_state = ERROR;
-
- reg = ENET_MAC_PHY_CTL;
- reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA);
- reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB);
-
- if(ENET_PHY_WRITE == direction){
- ENET_MAC_PHY_DATA = *pvalue;
- }
-
-
- ENET_MAC_PHY_CTL = reg;
- do{
- phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB);
- timeout++;
- }
- while((RESET != phy_flag) && (ENET_DELAY_TO != timeout));
-
- if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){
- enet_state = SUCCESS;
- }
-
- if(ENET_PHY_READ == direction){
- *pvalue = (uint16_t)ENET_MAC_PHY_DATA;
- }
-
- return enet_state;
- }
- ErrStatus enet_phyloopback_enable(void)
- {
- uint16_t temp_phy = 0U;
- ErrStatus phy_state = ERROR;
-
- enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
-
- temp_phy |= PHY_LOOPBACK;
-
- phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
- return phy_state;
- }
- ErrStatus enet_phyloopback_disable(void)
- {
- uint16_t temp_phy = 0U;
- ErrStatus phy_state = ERROR;
-
- enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
-
- temp_phy &= (uint16_t)~PHY_LOOPBACK;
-
- phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
- return phy_state;
- }
- void enet_forward_feature_enable(uint32_t feature)
- {
- uint32_t mask;
-
- mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES)));
- ENET_MAC_CFG |= mask;
-
- mask = (feature & (~(ENET_AUTO_PADCRC_DROP)));
- ENET_DMA_CTL |= (mask >> 2);
- }
- void enet_forward_feature_disable(uint32_t feature)
- {
- uint32_t mask;
-
- mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES)));
- ENET_MAC_CFG &= ~mask;
-
- mask = (feature & (~(ENET_AUTO_PADCRC_DROP)));
- ENET_DMA_CTL &= ~(mask >> 2);
- }
-
- void enet_filter_feature_enable(uint32_t feature)
- {
- ENET_MAC_FRMF |= feature;
- }
- void enet_filter_feature_disable(uint32_t feature)
- {
- ENET_MAC_FRMF &= ~feature;
- }
- ErrStatus enet_pauseframe_generate(void)
- {
- ErrStatus enet_state =ERROR;
- uint32_t temp = 0U;
-
- temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA;
- if(RESET == temp){
- ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA;
- enet_state = SUCCESS;
- }
- return enet_state;
- }
- void enet_pauseframe_detect_config(uint32_t detect)
- {
- ENET_MAC_FCTL &= ~ENET_MAC_FCTL_UPFDT;
- ENET_MAC_FCTL |= detect;
- }
- void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold)
- {
- ENET_MAC_FCTL &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_PLTS);
- ENET_MAC_FCTL |= (MAC_FCTL_PTM(pausetime) | pause_threshold);
- }
- void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active)
- {
- ENET_MAC_FCTH = ((deactive | active) >> 8);
- }
- void enet_flowcontrol_feature_enable(uint32_t feature)
- {
- if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){
- ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE;
- }
- feature &= ~ENET_ZERO_QUANTA_PAUSE;
- ENET_MAC_FCTL |= feature;
- }
- void enet_flowcontrol_feature_disable(uint32_t feature)
- {
- if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){
- ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE;
- }
- feature &= ~ENET_ZERO_QUANTA_PAUSE;
- ENET_MAC_FCTL &= ~feature;
- }
- uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction)
- {
- uint32_t reval;
- reval = (uint32_t)(ENET_DMA_STAT & (uint32_t)direction);
- return reval;
- }
- void enet_dmaprocess_resume(enet_dmadirection_enum direction)
- {
- if(ENET_DMA_TX == direction){
- ENET_DMA_TPEN = 0U;
- }else{
- ENET_DMA_RPEN = 0U;
- }
- }
- void enet_rxprocess_check_recovery(void)
- {
- uint32_t status;
-
- status = dma_current_rxdesc->status;
- status &= ENET_RDES0_DAV;
-
-
- if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) &&
- (ENET_RDES0_DAV == status)){
- dma_current_rxdesc = (enet_descriptors_struct*)ENET_DMA_CRDADDR;
- }
- }
- ErrStatus enet_txfifo_flush(void)
- {
- uint32_t flush_state;
- uint32_t timeout = 0U;
- ErrStatus enet_state = ERROR;
-
-
- ENET_DMA_CTL |= ENET_DMA_CTL_FTF;
-
- do{
- flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF;
- timeout++;
- }while((RESET != flush_state) && (timeout < ENET_DELAY_TO));
-
- if(RESET == flush_state){
- enet_state = SUCCESS;
- }
-
- return enet_state;
- }
- uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get)
- {
- uint32_t reval = 0U;
- reval = REG32((ENET) +(uint32_t)addr_get);
- return reval;
- }
- uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get)
- {
- uint32_t reval = 0xFFFFFFFFU;
- switch(info_get){
- case RXDESC_BUFFER_1_SIZE:
- reval = GET_RDES1_RB1S(desc->control_buffer_size);
- break;
- case RXDESC_BUFFER_2_SIZE:
- reval = GET_RDES1_RB2S(desc->control_buffer_size);
- break;
- case RXDESC_FRAME_LENGTH:
- reval = GET_RDES0_FRML(desc->status);
- if(reval > 4U){
- reval = reval - 4U;
- }else{
- reval = 0U;
- }
- break;
- case RXDESC_BUFFER_1_ADDR:
- reval = desc->buffer1_addr;
- break;
- case TXDESC_BUFFER_1_ADDR:
- reval = desc->buffer1_addr;
- break;
- case TXDESC_COLLISION_COUNT:
- reval = GET_TDES0_COCNT(desc->status);
- break;
- default:
- break;
- }
- return reval;
- }
- void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop)
- {
- uint32_t temp_counter = 0U;
-
- temp_counter = ENET_DMA_MFBOCNT;
- *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter);
- *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter);
- }
- FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag)
- {
- FlagStatus enet_flag = RESET;
-
- if ((uint32_t)RESET != (desc->status & desc_flag)){
- enet_flag = SET;
- }
- return enet_flag;
- }
- void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag)
- {
- desc->status |= desc_flag;
- }
- void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag)
- {
- desc->status &= ~desc_flag;
- }
- void enet_desc_receive_complete_bit_enable(enet_descriptors_struct *desc)
- {
- desc->control_buffer_size &= ~ENET_RDES1_DINTC;
- }
- void enet_desc_receive_complete_bit_disable(enet_descriptors_struct *desc)
- {
- desc->control_buffer_size |= ENET_RDES1_DINTC;
- }
- void enet_rxframe_drop(void)
- {
-
- dma_current_rxdesc->status = ENET_RDES0_DAV;
-
-
- if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
- if(NULL != dma_current_ptp_rxdesc){
- dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr);
-
- if(0U != dma_current_ptp_rxdesc->status){
-
- dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
- }else{
-
- dma_current_ptp_rxdesc++;
- }
- }else{
- dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr);
- }
-
- }else{
-
- if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
-
- dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
- if(NULL != dma_current_ptp_rxdesc){
- dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
- }
- }else{
-
- dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
- if(NULL != dma_current_ptp_rxdesc){
- dma_current_ptp_rxdesc++;
- }
- }
- }
- }
- void enet_dma_feature_enable(uint32_t feature)
- {
- ENET_DMA_CTL |= feature;
- }
- void enet_dma_feature_disable(uint32_t feature)
- {
- ENET_DMA_CTL &= ~feature;
- }
- void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab)
- {
- uint32_t num = 0U, count = 0U, maxsize = 0U;
- uint32_t desc_status = 0U, desc_bufsize = 0U;
- enet_descriptors_struct *desc, *desc_tab;
- uint8_t *buf;
-
-
- if (ENET_DMA_TX == direction){
-
- desc_tab = txdesc_tab;
- buf = &tx_buff[0][0];
- count = ENET_TXBUF_NUM;
- maxsize = ENET_TXBUF_SIZE;
-
-
- desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN;
-
-
- ENET_DMA_TDTADDR = (uint32_t)desc_tab;
- dma_current_txdesc = desc_tab;
- dma_current_ptp_txdesc = desc_ptptab;
- }else{
-
-
- desc_tab = rxdesc_tab;
- buf = &rx_buff[0][0];
- count = ENET_RXBUF_NUM;
- maxsize = ENET_RXBUF_SIZE;
-
-
- desc_status = ENET_RDES0_DAV;
-
- desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE;
-
-
- ENET_DMA_RDTADDR = (uint32_t)desc_tab;
- dma_current_rxdesc = desc_tab;
- dma_current_ptp_rxdesc = desc_ptptab;
- }
-
-
- for(num = 0U; num < count; num++){
-
- desc = desc_tab + num;
-
- desc->status = desc_status;
- desc->control_buffer_size = desc_bufsize;
- desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
-
-
- if(num < (count - 1U)){
-
- desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U);
- }else{
-
-
- desc->buffer2_next_desc_addr = (uint32_t)desc_tab;
- }
-
- (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr;
- (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr;
- }
-
- (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab;
- }
- void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab)
- {
- uint32_t num = 0U, count = 0U, maxsize = 0U;
- uint32_t desc_status = 0U, desc_bufsize = 0U;
- enet_descriptors_struct *desc, *desc_tab;
- uint8_t *buf;
-
- ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL;
- ENET_DMA_BCTL |= DMA_BCTL_DPSL(0);
-
-
- if (ENET_DMA_TX == direction){
-
- desc_tab = txdesc_tab;
- buf = &tx_buff[0][0];
- count = ENET_TXBUF_NUM;
- maxsize = ENET_TXBUF_SIZE;
-
-
- desc_status = ENET_TDES0_TTSEN;
-
-
- ENET_DMA_TDTADDR = (uint32_t)desc_tab;
- dma_current_txdesc = desc_tab;
- dma_current_ptp_txdesc = desc_ptptab;
- }else{
-
-
- desc_tab = rxdesc_tab;
- buf = &rx_buff[0][0];
- count = ENET_RXBUF_NUM;
- maxsize = ENET_RXBUF_SIZE;
-
-
- desc_status = ENET_RDES0_DAV;
-
- desc_bufsize = (uint32_t)ENET_RXBUF_SIZE;
-
-
- ENET_DMA_RDTADDR = (uint32_t)desc_tab;
- dma_current_rxdesc = desc_tab;
- dma_current_ptp_rxdesc = desc_ptptab;
- }
-
-
- for(num = 0U; num < count; num++){
-
- desc = desc_tab + num;
-
- desc->status = desc_status;
- desc->control_buffer_size = desc_bufsize;
- desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
-
-
- if(num == (count - 1U)){
- if (ENET_DMA_TX == direction){
-
- desc->status |= ENET_TDES0_TERM;
- }else{
-
- desc->control_buffer_size |= ENET_RDES1_RERM;
- }
- }
-
- (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr;
- (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr;
- }
-
- (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab;
- }
- ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[])
- {
- uint32_t offset = 0U, size = 0U;
-
-
- if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){
- return ERROR;
- }
-
-
- if(NULL != buffer){
-
- if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) &&
- ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) &&
- ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){
-
-
- size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U;
-
-
- if(size > bufsize){
- return ERROR;
- }
-
- for(offset = 0U; offset < size; offset++){
- (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset));
- }
-
- }else{
- return ERROR;
- }
- }
-
- timestamp[0] = dma_current_rxdesc->buffer1_addr;
- timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr;
- dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ;
- dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr;
-
-
- dma_current_rxdesc->status = ENET_RDES0_DAV;
-
-
- if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){
-
- ENET_DMA_STAT = ENET_DMA_STAT_RBU;
-
- ENET_DMA_RPEN = 0U;
- }
-
-
-
- if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
- dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr);
-
- if(0U != dma_current_ptp_rxdesc->status){
-
- dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
- }else{
-
- dma_current_ptp_rxdesc++;
- }
- }else{
-
- if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
-
- dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
-
- dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
- }else{
-
- dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
- dma_current_ptp_rxdesc ++;
- }
- }
- return SUCCESS;
- }
- ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[])
- {
- uint32_t offset = 0U, timeout = 0U;
- uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag;
-
-
- if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){
- return ERROR;
- }
-
- if(length > ENET_MAX_FRAME_SIZE){
- return ERROR;
- }
-
-
- if(NULL != buffer){
-
- for(offset = 0U; offset < length; offset++){
- (*(__IO uint8_t *) (uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset));
- }
- }
-
- dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF);
-
- dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG;
-
- dma_current_txdesc->status |= ENET_TDES0_DAV;
-
-
- dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU);
- dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU);
-
- if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){
-
- ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag);
-
- ENET_DMA_TPEN = 0U;
- }
-
-
- if(NULL != timestamp){
-
- do{
- tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS);
- timeout++;
- }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO));
-
-
- if(ENET_DELAY_TO == timeout){
- return ERROR;
- }
-
-
- dma_current_txdesc->status &= ~ENET_TDES0_TTMSS;
-
- timestamp[0] = dma_current_txdesc->buffer1_addr;
- timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr;
- }
- dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ;
- dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr;
-
-
- if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){
- dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr);
-
- if(0U != dma_current_ptp_txdesc->status){
-
- dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status);
- }else{
-
- dma_current_ptp_txdesc++;
- }
- }else{
-
- if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){
-
- dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR);
-
- dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status);
- }else{
-
- dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
- dma_current_ptp_txdesc ++;
- }
- }
- return SUCCESS;
- }
- void enet_wum_filter_register_pointer_reset(void)
- {
- ENET_MAC_WUM |= ENET_MAC_WUM_WUFFRPR;
- }
- void enet_wum_filter_config(uint32_t pdata[])
- {
- uint32_t num = 0U;
-
-
- for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){
- ENET_MAC_RWFF = pdata[num];
- }
- }
- void enet_wum_feature_enable(uint32_t feature)
- {
- ENET_MAC_WUM |= feature;
- }
- void enet_wum_feature_disable(uint32_t feature)
- {
- ENET_MAC_WUM &= (~feature);
- }
- void enet_msc_counters_reset(void)
- {
-
- ENET_MSC_CTL |= ENET_MSC_CTL_CTR;
- }
- void enet_msc_feature_enable(uint32_t feature)
- {
- ENET_MSC_CTL |= feature;
- }
- void enet_msc_feature_disable(uint32_t feature)
- {
- ENET_MSC_CTL &= (~feature);
- }
- uint32_t enet_msc_counters_get(enet_msc_counter_enum counter)
- {
- uint32_t reval;
-
- reval = REG32((ENET + (uint32_t)counter));
-
- return reval;
- }
- uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond)
- {
- uint64_t val = subsecond * 1000000000Ull;
- val >>= 31;
- return (uint32_t)val;
- }
- uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond)
- {
- uint64_t val = nanosecond * 0x80000000Ull;
- val /= 1000000000U;
- return (uint32_t)val;
- }
- void enet_ptp_feature_enable(uint32_t feature)
- {
- ENET_PTP_TSCTL |= feature;
- }
- void enet_ptp_feature_disable(uint32_t feature)
- {
- ENET_PTP_TSCTL &= ~feature;
- }
- ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func)
- {
- uint32_t temp_config = 0U, temp_state = 0U;
- uint32_t timeout = 0U;
- ErrStatus enet_state = SUCCESS;
- switch(func){
- case ENET_PTP_ADDEND_UPDATE:
-
- do{
- temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU;
- timeout++;
- }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
-
- if(ENET_DELAY_TO == timeout){
- enet_state = ERROR;
- }else{
- ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU;
- }
- break;
- case ENET_PTP_SYSTIME_UPDATE:
-
- do{
- temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI);
- timeout++;
- }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
-
- if(ENET_DELAY_TO == timeout){
- enet_state = ERROR;
- }else{
- ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU;
- }
- break;
- case ENET_PTP_SYSTIME_INIT:
-
- do{
- temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI;
- timeout++;
- }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
-
- if(ENET_DELAY_TO == timeout){
- enet_state = ERROR;
- }else{
- ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI;
- }
- break;
- default:
- temp_config = (uint32_t)func & (~BIT(31));
- if(RESET != ((uint32_t)func & BIT(31))){
- ENET_PTP_TSCTL |= temp_config;
- }else{
- ENET_PTP_TSCTL &= ~temp_config;
- }
- break;
- }
- return enet_state;
- }
- void enet_ptp_subsecond_increment_config(uint32_t subsecond)
- {
- ENET_PTP_SSINC = PTP_SSINC_STMSSI(subsecond);
- }
- void enet_ptp_timestamp_addend_config(uint32_t add)
- {
- ENET_PTP_TSADDEND = add;
- }
- void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond)
- {
- ENET_PTP_TSUH = second;
- ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond);
- }
- void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond)
- {
- ENET_PTP_ETH = second;
- ENET_PTP_ETL = nanosecond;
- }
- void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct)
- {
- uint32_t temp_sec = 0U, temp_subs = 0U;
-
- temp_sec = (uint32_t)ENET_PTP_TSH;
- temp_subs = (uint32_t)ENET_PTP_TSL;
-
-
- systime_struct->second = temp_sec;
- systime_struct->nanosecond = GET_PTP_TSL_STMSS(temp_subs);
- systime_struct->nanosecond = enet_ptp_subsecond_2_nanosecond(systime_struct->nanosecond);
- systime_struct->sign = GET_PTP_TSL_STS(temp_subs);
- }
- void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg)
- {
-
- enet_interrupt_disable(ENET_MAC_INT_TMSTIM);
-
- enet_ptp_feature_enable(ENET_RXTX_TIMESTAMP);
-
- enet_ptp_subsecond_increment_config(accuracy_cfg);
- if(ENET_PTP_FINEMODE == updatemethod){
-
- enet_ptp_timestamp_addend_config(carry_cfg);
- enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
-
- while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_ADDEND_UPDATE)){
- }
- }
-
- enet_ptp_timestamp_function_config((enet_ptp_function_enum)updatemethod);
-
- enet_ptp_timestamp_update_config(ENET_PTP_ADD_TO_TIME, init_sec, init_subsec);
- enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT);
- }
- void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg)
- {
-
- enet_ptp_timestamp_addend_config((uint32_t)carry_cfg);
- enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
- }
- void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct)
- {
- uint32_t subsecond_val;
- uint32_t carry_cfg;
- subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond);
-
-
- carry_cfg = ENET_PTP_TSADDEND_TMSA;
-
- enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val);
- enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_UPDATE);
-
- while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_UPDATE)){
- }
-
-
- enet_ptp_timestamp_addend_config(carry_cfg);
- enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
- }
- void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct)
- {
- uint32_t subsecond_val;
- subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond);
-
- enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val);
- enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT);
-
-
- while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_INIT)){
- }
- }
- FlagStatus enet_ptp_flag_get(uint32_t flag)
- {
- FlagStatus bitstatus = RESET;
- if ((uint32_t)RESET != (ENET_PTP_TSCTL & flag)){
- bitstatus = SET;
- }
-
- return bitstatus;
- }
- void enet_initpara_reset(void)
- {
- enet_initpara.option_enable = 0U;
- enet_initpara.forward_frame = 0U;
- enet_initpara.dmabus_mode = 0U;
- enet_initpara.dma_maxburst = 0U;
- enet_initpara.dma_arbitration = 0U;
- enet_initpara.store_forward_mode = 0U;
- enet_initpara.dma_function = 0U;
- enet_initpara.vlan_config = 0U;
- enet_initpara.flow_control = 0U;
- enet_initpara.hashtable_high = 0U;
- enet_initpara.hashtable_low = 0U;
- enet_initpara.framesfilter_mode = 0U;
- enet_initpara.halfduplex_param = 0U;
- enet_initpara.timer_config = 0U;
- enet_initpara.interframegap = 0U;
- }
- static void enet_default_init(void)
- {
- uint32_t reg_value = 0U;
-
-
- reg_value = ENET_MAC_CFG;
- reg_value &= MAC_CFG_MASK;
- reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \
- | ENET_SPEEDMODE_10M |ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \
- | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \
- | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \
- | ENET_DEFERRALCHECK_DISABLE \
- | ENET_AUTO_PADCRC_DROP_DISABLE \
- | ENET_CHECKSUMOFFLOAD_DISABLE;
- ENET_MAC_CFG = reg_value;
-
-
- ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE |ENET_DEST_FILTER_INVERSE_DISABLE \
- |ENET_MULTICAST_FILTER_PERFECT |ENET_UNICAST_FILTER_PERFECT \
- |ENET_PCFRM_PREVENT_ALL |ENET_BROADCASTFRAMES_ENABLE \
- |ENET_PROMISCUOUS_DISABLE |ENET_RX_FILTER_ENABLE;
-
- ENET_MAC_HLH = 0x0U;
-
- ENET_MAC_HLL = 0x0U;
-
- reg_value = ENET_MAC_FCTL;
- reg_value &= MAC_FCTL_MASK;
- reg_value |= MAC_FCTL_PTM(0) |ENET_ZERO_QUANTA_PAUSE_DISABLE \
- |ENET_PAUSETIME_MINUS4 |ENET_UNIQUE_PAUSEDETECT \
- |ENET_RX_FLOWCONTROL_DISABLE |ENET_TX_FLOWCONTROL_DISABLE;
- ENET_MAC_FCTL = reg_value;
-
- ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT |MAC_VLT_VLTI(0);
-
-
- reg_value = ENET_DMA_CTL;
- reg_value &= DMA_CTL_MASK;
- reg_value |= ENET_TCPIP_CKSUMERROR_DROP |ENET_RX_MODE_STOREFORWARD \
- |ENET_FLUSH_RXFRAME_ENABLE |ENET_TX_MODE_STOREFORWARD \
- |ENET_TX_THRESHOLD_64BYTES |ENET_RX_THRESHOLD_64BYTES \
- |ENET_SECONDFRAME_OPT_DISABLE;
- ENET_DMA_CTL = reg_value;
-
- reg_value = ENET_DMA_BCTL;
- reg_value &= DMA_BCTL_MASK;
- reg_value = ENET_ADDRESS_ALIGN_ENABLE |ENET_ARBITRATION_RXTX_2_1 \
- |ENET_RXDP_32BEAT |ENET_PGBL_32BEAT |ENET_RXTX_DIFFERENT_PGBL \
- |ENET_FIXED_BURST_ENABLE;
- ENET_DMA_BCTL = reg_value;
- }
- #ifndef USE_DELAY
- static void enet_delay(uint32_t ncount)
- {
- __IO uint32_t delay_time = 0U;
-
- for(delay_time = ncount; delay_time != 0U; delay_time--){
- }
- }
- #endif
- #endif
|