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- #ifndef GD32F10X_RCU_H
- #define GD32F10X_RCU_H
- #include "gd32f10x.h"
- #define RCU RCU_BASE
- #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define RCU_CTL REG32(RCU + 0x00U)
- #define RCU_CFG0 REG32(RCU + 0x04U)
- #define RCU_INT REG32(RCU + 0x08U)
- #define RCU_APB2RST REG32(RCU + 0x0CU)
- #define RCU_APB1RST REG32(RCU + 0x10U)
- #define RCU_AHBEN REG32(RCU + 0x14U)
- #define RCU_APB2EN REG32(RCU + 0x18U)
- #define RCU_APB1EN REG32(RCU + 0x1CU)
- #define RCU_BDCTL REG32(RCU + 0x20U)
- #define RCU_RSTSCK REG32(RCU + 0x24U)
- #define RCU_DSV REG32(RCU + 0x34U)
- #elif defined(GD32F10X_CL)
- #define RCU_CTL REG32(RCU + 0x00U)
- #define RCU_CFG0 REG32(RCU + 0x04U)
- #define RCU_INT REG32(RCU + 0x08U)
- #define RCU_APB2RST REG32(RCU + 0x0CU)
- #define RCU_APB1RST REG32(RCU + 0x10U)
- #define RCU_AHBEN REG32(RCU + 0x14U)
- #define RCU_APB2EN REG32(RCU + 0x18U)
- #define RCU_APB1EN REG32(RCU + 0x1CU)
- #define RCU_BDCTL REG32(RCU + 0x20U)
- #define RCU_RSTSCK REG32(RCU + 0x24U)
- #define RCU_AHBRST REG32(RCU + 0x28U)
- #define RCU_CFG1 REG32(RCU + 0x2CU)
- #define RCU_DSV REG32(RCU + 0x34U)
- #endif
- #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define RCU_CTL_IRC8MEN BIT(0)
- #define RCU_CTL_IRC8MSTB BIT(1)
- #define RCU_CTL_IRC8MADJ BITS(3,7)
- #define RCU_CTL_IRC8MCALIB BITS(8,15)
- #define RCU_CTL_HXTALEN BIT(16)
- #define RCU_CTL_HXTALSTB BIT(17)
- #define RCU_CTL_HXTALBPS BIT(18)
- #define RCU_CTL_CKMEN BIT(19)
- #define RCU_CTL_PLLEN BIT(24)
- #define RCU_CTL_PLLSTB BIT(25)
- #elif defined(GD32F10X_CL)
- #define RCU_CTL_IRC8MEN BIT(0)
- #define RCU_CTL_IRC8MSTB BIT(1)
- #define RCU_CTL_IRC8MADJ BITS(3,7)
- #define RCU_CTL_IRC8MCALIB BITS(8,15)
- #define RCU_CTL_HXTALEN BIT(16)
- #define RCU_CTL_HXTALSTB BIT(17)
- #define RCU_CTL_HXTALBPS BIT(18)
- #define RCU_CTL_CKMEN BIT(19)
- #define RCU_CTL_PLLEN BIT(24)
- #define RCU_CTL_PLLSTB BIT(25)
- #define RCU_CTL_PLL1EN BIT(26)
- #define RCU_CTL_PLL1STB BIT(27)
- #define RCU_CTL_PLL2EN BIT(28)
- #define RCU_CTL_PLL2STB BIT(29)
- #endif
- #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define RCU_CFG0_SCS BITS(0,1)
- #define RCU_CFG0_SCSS BITS(2,3)
- #define RCU_CFG0_AHBPSC BITS(4,7)
- #define RCU_CFG0_APB1PSC BITS(8,10)
- #define RCU_CFG0_APB2PSC BITS(11,13)
- #define RCU_CFG0_ADCPSC BITS(14,15)
- #define RCU_CFG0_PLLSEL BIT(16)
- #define RCU_CFG0_PREDV0 BIT(17)
- #define RCU_CFG0_PLLMF BITS(18,21)
- #define RCU_CFG0_USBDPSC BITS(22,23)
- #define RCU_CFG0_CKOUT0SEL BITS(24,26)
- #define RCU_CFG0_PLLMF_4 BIT(27)
- #define RCU_CFG0_ADCPSC_2 BIT(28)
- #elif defined(GD32F10X_CL)
- #define RCU_CFG0_SCS BITS(0,1)
- #define RCU_CFG0_SCSS BITS(2,3)
- #define RCU_CFG0_AHBPSC BITS(4,7)
- #define RCU_CFG0_APB1PSC BITS(8,10)
- #define RCU_CFG0_APB2PSC BITS(11,13)
- #define RCU_CFG0_ADCPSC BITS(14,15)
- #define RCU_CFG0_PLLSEL BIT(16)
- #define RCU_CFG0_PREDV0_LSB BIT(17)
- #define RCU_CFG0_PLLMF BITS(18,21)
- #define RCU_CFG0_USBFSPSC BITS(22,23)
- #define RCU_CFG0_CKOUT0SEL BITS(24,27)
- #define RCU_CFG0_ADCPSC_2 BIT(28)
- #define RCU_CFG0_PLLMF_4 BIT(29)
- #endif
- #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define RCU_INT_IRC40KSTBIF BIT(0)
- #define RCU_INT_LXTALSTBIF BIT(1)
- #define RCU_INT_IRC8MSTBIF BIT(2)
- #define RCU_INT_HXTALSTBIF BIT(3)
- #define RCU_INT_PLLSTBIF BIT(4)
- #define RCU_INT_CKMIF BIT(7)
- #define RCU_INT_IRC40KSTBIE BIT(8)
- #define RCU_INT_LXTALSTBIE BIT(9)
- #define RCU_INT_IRC8MSTBIE BIT(10)
- #define RCU_INT_HXTALSTBIE BIT(11)
- #define RCU_INT_PLLSTBIE BIT(12)
- #define RCU_INT_IRC40KSTBIC BIT(16)
- #define RCU_INT_LXTALSTBIC BIT(17)
- #define RCU_INT_IRC8MSTBIC BIT(18)
- #define RCU_INT_HXTALSTBIC BIT(19)
- #define RCU_INT_PLLSTBIC BIT(20)
- #define RCU_INT_CKMIC BIT(23)
- #elif defined(GD32F10X_CL)
- #define RCU_INT_IRC40KSTBIF BIT(0)
- #define RCU_INT_LXTALSTBIF BIT(1)
- #define RCU_INT_IRC8MSTBIF BIT(2)
- #define RCU_INT_HXTALSTBIF BIT(3)
- #define RCU_INT_PLLSTBIF BIT(4)
- #define RCU_INT_PLL1STBIF BIT(5)
- #define RCU_INT_PLL2STBIF BIT(6)
- #define RCU_INT_CKMIF BIT(7)
- #define RCU_INT_IRC40KSTBIE BIT(8)
- #define RCU_INT_LXTALSTBIE BIT(9)
- #define RCU_INT_IRC8MSTBIE BIT(10)
- #define RCU_INT_HXTALSTBIE BIT(11)
- #define RCU_INT_PLLSTBIE BIT(12)
- #define RCU_INT_PLL1STBIE BIT(13)
- #define RCU_INT_PLL2STBIE BIT(14)
- #define RCU_INT_IRC40KSTBIC BIT(16)
- #define RCU_INT_LXTALSTBIC BIT(17)
- #define RCU_INT_IRC8MSTBIC BIT(18)
- #define RCU_INT_HXTALSTBIC BIT(19)
- #define RCU_INT_PLLSTBIC BIT(20)
- #define RCU_INT_PLL1STBIC BIT(21)
- #define RCU_INT_PLL2STBIC BIT(22)
- #define RCU_INT_CKMIC BIT(23)
- #endif
- #define RCU_APB2RST_AFRST BIT(0)
- #define RCU_APB2RST_PARST BIT(2)
- #define RCU_APB2RST_PBRST BIT(3)
- #define RCU_APB2RST_PCRST BIT(4)
- #define RCU_APB2RST_PDRST BIT(5)
- #define RCU_APB2RST_PERST BIT(6)
- #define RCU_APB2RST_PFRST BIT(7)
- #define RCU_APB2RST_PGRST BIT(8)
- #define RCU_APB2RST_ADC0RST BIT(9)
- #define RCU_APB2RST_ADC1RST BIT(10)
- #define RCU_APB2RST_TIMER0RST BIT(11)
- #define RCU_APB2RST_SPI0RST BIT(12)
- #define RCU_APB2RST_TIMER7RST BIT(13)
- #define RCU_APB2RST_USART0RST BIT(14)
- #ifndef GD32F10X_CL
- #define RCU_APB2RST_ADC2RST BIT(15)
- #endif
- #ifdef GD32F10X_XD
- #define RCU_APB2RST_TIMER8RST BIT(19)
- #define RCU_APB2RST_TIMER9RST BIT(20)
- #define RCU_APB2RST_TIMER10RST BIT(21)
- #endif
- #define RCU_APB1RST_TIMER1RST BIT(0)
- #define RCU_APB1RST_TIMER2RST BIT(1)
- #define RCU_APB1RST_TIMER3RST BIT(2)
- #define RCU_APB1RST_TIMER4RST BIT(3)
- #define RCU_APB1RST_TIMER5RST BIT(4)
- #define RCU_APB1RST_TIMER6RST BIT(5)
- #ifdef GD32F10X_XD
- #define RCU_APB1RST_TIMER11RST BIT(6)
- #define RCU_APB1RST_TIMER12RST BIT(7)
- #define RCU_APB1RST_TIMER13RST BIT(8)
- #endif
- #define RCU_APB1RST_WWDGTRST BIT(11)
- #define RCU_APB1RST_SPI1RST BIT(14)
- #define RCU_APB1RST_SPI2RST BIT(15)
- #define RCU_APB1RST_USART1RST BIT(17)
- #define RCU_APB1RST_USART2RST BIT(18)
- #define RCU_APB1RST_UART3RST BIT(19)
- #define RCU_APB1RST_UART4RST BIT(20)
- #define RCU_APB1RST_I2C0RST BIT(21)
- #define RCU_APB1RST_I2C1RST BIT(22)
- #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define RCU_APB1RST_USBDRST BIT(23)
- #endif
- #define RCU_APB1RST_CAN0RST BIT(25)
- #ifdef GD32F10X_CL
- #define RCU_APB1RST_CAN1RST BIT(26)
- #endif
- #define RCU_APB1RST_BKPIRST BIT(27)
- #define RCU_APB1RST_PMURST BIT(28)
- #define RCU_APB1RST_DACRST BIT(29)
- #define RCU_AHBEN_DMA0EN BIT(0)
- #define RCU_AHBEN_DMA1EN BIT(1)
- #define RCU_AHBEN_SRAMSPEN BIT(2)
- #define RCU_AHBEN_FMCSPEN BIT(4)
- #define RCU_AHBEN_CRCEN BIT(6)
- #define RCU_AHBEN_EXMCEN BIT(8)
- #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define RCU_AHBEN_SDIOEN BIT(10)
- #elif defined(GD32F10X_CL)
- #define RCU_AHBEN_USBFSEN BIT(12)
- #define RCU_AHBEN_ENETEN BIT(14)
- #define RCU_AHBEN_ENETTXEN BIT(15)
- #define RCU_AHBEN_ENETRXEN BIT(16)
- #endif
- #define RCU_APB2EN_AFEN BIT(0)
- #define RCU_APB2EN_PAEN BIT(2)
- #define RCU_APB2EN_PBEN BIT(3)
- #define RCU_APB2EN_PCEN BIT(4)
- #define RCU_APB2EN_PDEN BIT(5)
- #define RCU_APB2EN_PEEN BIT(6)
- #define RCU_APB2EN_PFEN BIT(7)
- #define RCU_APB2EN_PGEN BIT(8)
- #define RCU_APB2EN_ADC0EN BIT(9)
- #define RCU_APB2EN_ADC1EN BIT(10)
- #define RCU_APB2EN_TIMER0EN BIT(11)
- #define RCU_APB2EN_SPI0EN BIT(12)
- #define RCU_APB2EN_TIMER7EN BIT(13)
- #define RCU_APB2EN_USART0EN BIT(14)
- #ifndef GD32F10X_CL
- #define RCU_APB2EN_ADC2EN BIT(15)
- #endif
- #ifdef GD32F10X_XD
- #define RCU_APB2EN_TIMER8EN BIT(19)
- #define RCU_APB2EN_TIMER9EN BIT(20)
- #define RCU_APB2EN_TIMER10EN BIT(21)
- #endif
- #define RCU_APB1EN_TIMER1EN BIT(0)
- #define RCU_APB1EN_TIMER2EN BIT(1)
- #define RCU_APB1EN_TIMER3EN BIT(2)
- #define RCU_APB1EN_TIMER4EN BIT(3)
- #define RCU_APB1EN_TIMER5EN BIT(4)
- #define RCU_APB1EN_TIMER6EN BIT(5)
- #ifdef GD32F10X_XD
- #define RCU_APB1EN_TIMER11EN BIT(6)
- #define RCU_APB1EN_TIMER12EN BIT(7)
- #define RCU_APB1EN_TIMER13EN BIT(8)
- #endif
- #define RCU_APB1EN_WWDGTEN BIT(11)
- #define RCU_APB1EN_SPI1EN BIT(14)
- #define RCU_APB1EN_SPI2EN BIT(15)
- #define RCU_APB1EN_USART1EN BIT(17)
- #define RCU_APB1EN_USART2EN BIT(18)
- #define RCU_APB1EN_UART3EN BIT(19)
- #define RCU_APB1EN_UART4EN BIT(20)
- #define RCU_APB1EN_I2C0EN BIT(21)
- #define RCU_APB1EN_I2C1EN BIT(22)
- #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define RCU_APB1EN_USBDEN BIT(23)
- #endif
- #define RCU_APB1EN_CAN0EN BIT(25)
- #ifdef GD32F10X_CL
- #define RCU_APB1EN_CAN1EN BIT(26)
- #endif
- #define RCU_APB1EN_BKPIEN BIT(27)
- #define RCU_APB1EN_PMUEN BIT(28)
- #define RCU_APB1EN_DACEN BIT(29)
- #define RCU_BDCTL_LXTALEN BIT(0)
- #define RCU_BDCTL_LXTALSTB BIT(1)
- #define RCU_BDCTL_LXTALBPS BIT(2)
- #define RCU_BDCTL_RTCSRC BITS(8,9)
- #define RCU_BDCTL_RTCEN BIT(15)
- #define RCU_BDCTL_BKPRST BIT(16)
- #define RCU_RSTSCK_IRC40KEN BIT(0)
- #define RCU_RSTSCK_IRC40KSTB BIT(1)
- #define RCU_RSTSCK_RSTFC BIT(24)
- #define RCU_RSTSCK_EPRSTF BIT(26)
- #define RCU_RSTSCK_PORRSTF BIT(27)
- #define RCU_RSTSCK_SWRSTF BIT(28)
- #define RCU_RSTSCK_FWDGTRSTF BIT(29)
- #define RCU_RSTSCK_WWDGTRSTF BIT(30)
- #define RCU_RSTSCK_LPRSTF BIT(31)
- #ifdef GD32F10X_CL
- #define RCU_AHBRST_USBFSRST BIT(12)
- #define RCU_AHBRST_ENETRST BIT(14)
- #endif
- #if defined(GD32F10X_CL)
- #define RCU_CFG1_PREDV0 BITS(0,3)
- #define RCU_CFG1_PREDV1 BITS(4,7)
- #define RCU_CFG1_PLL1MF BITS(8,11)
- #define RCU_CFG1_PLL2MF BITS(12,15)
- #define RCU_CFG1_PREDV0SEL BIT(16)
- #define RCU_CFG1_I2S1SEL BIT(17)
- #define RCU_CFG1_I2S2SEL BIT(18)
- #endif
- #define RCU_DSV_DSLPVS BITS(0,2)
- #define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
- #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6)))
- #define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
- #define AHBEN_REG_OFFSET 0x14U
- #define APB1EN_REG_OFFSET 0x1CU
- #define APB2EN_REG_OFFSET 0x18U
- #define AHBRST_REG_OFFSET 0x28U
- #define APB1RST_REG_OFFSET 0x10U
- #define APB2RST_REG_OFFSET 0x0CU
- #define RSTSCK_REG_OFFSET 0x24U
- #define CTL_REG_OFFSET 0x00U
- #define BDCTL_REG_OFFSET 0x20U
- #define INT_REG_OFFSET 0x08U
- #define CFG0_REG_OFFSET 0x04U
- #define CFG1_REG_OFFSET 0x2CU
- typedef enum
- {
-
- RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U),
- RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U),
- RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U),
- RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U),
- #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
- RCU_SDIO = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 10U),
- #elif defined(GD32F10X_CL)
- RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U),
- RCU_ENET = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 14U),
- RCU_ENETTX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 15U),
- RCU_ENETRX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 16U),
- #endif
-
-
- RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U),
- RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U),
- RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U),
- RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U),
- RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U),
- RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U),
- #if defined(GD32F10X_XD)
- RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U),
- RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U),
- RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U),
- #endif
- RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U),
- RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U),
- RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U),
- RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U),
- RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U),
- RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U),
- RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U),
- RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U),
- RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U),
- #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
- RCU_USBD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U),
- #endif
- RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U),
- #ifdef GD32F10X_CL
- RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U),
- #endif
- RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U),
- RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U),
- RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U),
- RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U),
-
-
- RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U),
- RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U),
- RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U),
- RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U),
- RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U),
- RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U),
- RCU_GPIOF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 7U),
- RCU_GPIOG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U),
- RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U),
- RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U),
- RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U),
- RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U),
- RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U),
- RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U),
- #ifndef GD32F10X_CL
- RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 15U),
- #endif
- #ifdef GD32F10X_XD
- RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U),
- RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U),
- RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U),
- #endif
- }rcu_periph_enum;
- typedef enum
- {
-
- RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U),
- RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U),
- }rcu_periph_sleep_enum;
- typedef enum
- {
-
- #ifdef GD32F10X_CL
- RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U),
- RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U),
- #endif
-
-
- RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U),
- RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U),
- RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U),
- RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U),
- RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U),
- RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U),
- #ifdef GD32F10X_XD
- RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U),
- RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U),
- RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U),
- #endif
- RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U),
- RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U),
- RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U),
- RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U),
- RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U),
- RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U),
- RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U),
- RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U),
- RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U),
- #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
- RCU_USBDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U),
- #endif
- RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U),
- #ifdef GD32F10X_CL
- RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U),
- #endif
- RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U),
- RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U),
- RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U),
-
-
- RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U),
- RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U),
- RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U),
- RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U),
- RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U),
- RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U),
- RCU_GPIOFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 7U),
- RCU_GPIOGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U),
- RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U),
- RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U),
- RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U),
- RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U),
- RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U),
- RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U),
- #ifndef GD32F10X_CL
- RCU_ADC2RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 15U),
- #endif
- #ifdef GD32F10X_XD
- RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U),
- RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U),
- RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U),
- #endif
- }rcu_periph_reset_enum;
- typedef enum
- {
-
- RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U),
- RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U),
- RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U),
- #ifdef GD32F10X_CL
- RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U),
- RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U),
- #endif
- RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U),
- RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U),
-
- RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U),
- RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U),
- RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U),
- RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U),
- RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U),
- RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U),
- }rcu_flag_enum;
- typedef enum
- {
- RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U),
- RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U),
- RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U),
- RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U),
- RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U),
- #ifdef GD32F10X_CL
- RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U),
- RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U),
- #endif
- RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U),
- }rcu_int_flag_enum;
- typedef enum
- {
- RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U),
- RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U),
- RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U),
- RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U),
- RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U),
- #ifdef GD32F10X_CL
- RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U),
- RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U),
- #endif
- RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U),
- }rcu_int_flag_clear_enum;
- typedef enum
- {
- RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U),
- RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U),
- RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U),
- RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U),
- RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U),
- #ifdef GD32F10X_CL
- RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U),
- RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U),
- #endif
- }rcu_int_enum;
- typedef enum
- {
- RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U),
- RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U),
- RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U),
- RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U),
- RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U),
- #ifdef GD32F10X_CL
- RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U),
- RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U),
- #endif
- }rcu_osci_type_enum;
- typedef enum
- {
- CK_SYS = 0,
- CK_AHB,
- CK_APB1,
- CK_APB2,
- }rcu_clock_freq_enum;
- #define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
- #define RCU_CKSYSSRC_IRC8M CFG0_SCS(0)
- #define RCU_CKSYSSRC_HXTAL CFG0_SCS(1)
- #define RCU_CKSYSSRC_PLL CFG0_SCS(2)
- #define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
- #define RCU_SCSS_IRC8M CFG0_SCSS(0)
- #define RCU_SCSS_HXTAL CFG0_SCSS(1)
- #define RCU_SCSS_PLL CFG0_SCSS(2)
- #define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
- #define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0)
- #define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8)
- #define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9)
- #define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10)
- #define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11)
- #define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12)
- #define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13)
- #define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14)
- #define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15)
- #define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
- #define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0)
- #define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4)
- #define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5)
- #define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6)
- #define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7)
- #define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11))
- #define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0)
- #define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4)
- #define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5)
- #define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6)
- #define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7)
- #define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U)
- #define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U)
- #define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U)
- #define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U)
- #define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U)
- #define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U)
- #define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U)
- #define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL
- #define PLLMF_4 RCU_CFG0_PLLMF_4
- #define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18))
- #define RCU_PLL_MUL2 CFG0_PLLMF(0)
- #define RCU_PLL_MUL3 CFG0_PLLMF(1)
- #define RCU_PLL_MUL4 CFG0_PLLMF(2)
- #define RCU_PLL_MUL5 CFG0_PLLMF(3)
- #define RCU_PLL_MUL6 CFG0_PLLMF(4)
- #define RCU_PLL_MUL7 CFG0_PLLMF(5)
- #define RCU_PLL_MUL8 CFG0_PLLMF(6)
- #define RCU_PLL_MUL9 CFG0_PLLMF(7)
- #define RCU_PLL_MUL10 CFG0_PLLMF(8)
- #define RCU_PLL_MUL11 CFG0_PLLMF(9)
- #define RCU_PLL_MUL12 CFG0_PLLMF(10)
- #define RCU_PLL_MUL13 CFG0_PLLMF(11)
- #define RCU_PLL_MUL14 CFG0_PLLMF(12)
- #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define RCU_PLL_MUL15 CFG0_PLLMF(13)
- #elif defined(GD32F10X_CL)
- #define RCU_PLL_MUL6_5 CFG0_PLLMF(13)
- #endif
- #define RCU_PLL_MUL16 CFG0_PLLMF(14)
- #define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0))
- #define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1))
- #define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2))
- #define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3))
- #define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4))
- #define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5))
- #define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6))
- #define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7))
- #define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8))
- #define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9))
- #define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10))
- #define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11))
- #define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12))
- #define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13))
- #define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14))
- #define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15))
- #define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22))
- #define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0)
- #define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1)
- #define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2)
- #define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3)
- #define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
- #define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0)
- #define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4)
- #define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5)
- #define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6)
- #define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7)
- #ifdef GD32F10X_CL
- #define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8)
- #define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9)
- #define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10)
- #define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11)
- #endif
- #define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
- #define RCU_RTCSRC_NONE BDCTL_RTCSRC(0)
- #define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1)
- #define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2)
- #define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3)
- #define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
- #define RCU_PREDV0_DIV1 CFG1_PREDV0(0)
- #define RCU_PREDV0_DIV2 CFG1_PREDV0(1)
- #define RCU_PREDV0_DIV3 CFG1_PREDV0(2)
- #define RCU_PREDV0_DIV4 CFG1_PREDV0(3)
- #define RCU_PREDV0_DIV5 CFG1_PREDV0(4)
- #define RCU_PREDV0_DIV6 CFG1_PREDV0(5)
- #define RCU_PREDV0_DIV7 CFG1_PREDV0(6)
- #define RCU_PREDV0_DIV8 CFG1_PREDV0(7)
- #define RCU_PREDV0_DIV9 CFG1_PREDV0(8)
- #define RCU_PREDV0_DIV10 CFG1_PREDV0(9)
- #define RCU_PREDV0_DIV11 CFG1_PREDV0(10)
- #define RCU_PREDV0_DIV12 CFG1_PREDV0(11)
- #define RCU_PREDV0_DIV13 CFG1_PREDV0(12)
- #define RCU_PREDV0_DIV14 CFG1_PREDV0(13)
- #define RCU_PREDV0_DIV15 CFG1_PREDV0(14)
- #define RCU_PREDV0_DIV16 CFG1_PREDV0(15)
- #define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
- #define RCU_PREDV1_DIV1 CFG1_PREDV1(0)
- #define RCU_PREDV1_DIV2 CFG1_PREDV1(1)
- #define RCU_PREDV1_DIV3 CFG1_PREDV1(2)
- #define RCU_PREDV1_DIV4 CFG1_PREDV1(3)
- #define RCU_PREDV1_DIV5 CFG1_PREDV1(4)
- #define RCU_PREDV1_DIV6 CFG1_PREDV1(5)
- #define RCU_PREDV1_DIV7 CFG1_PREDV1(6)
- #define RCU_PREDV1_DIV8 CFG1_PREDV1(7)
- #define RCU_PREDV1_DIV9 CFG1_PREDV1(8)
- #define RCU_PREDV1_DIV10 CFG1_PREDV1(9)
- #define RCU_PREDV1_DIV11 CFG1_PREDV1(10)
- #define RCU_PREDV1_DIV12 CFG1_PREDV1(11)
- #define RCU_PREDV1_DIV13 CFG1_PREDV1(12)
- #define RCU_PREDV1_DIV14 CFG1_PREDV1(13)
- #define RCU_PREDV1_DIV15 CFG1_PREDV1(14)
- #define RCU_PREDV1_DIV16 CFG1_PREDV1(15)
- #define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
- #define RCU_PLL1_MUL8 CFG1_PLL1MF(6)
- #define RCU_PLL1_MUL9 CFG1_PLL1MF(7)
- #define RCU_PLL1_MUL10 CFG1_PLL1MF(8)
- #define RCU_PLL1_MUL11 CFG1_PLL1MF(9)
- #define RCU_PLL1_MUL12 CFG1_PLL1MF(10)
- #define RCU_PLL1_MUL13 CFG1_PLL1MF(11)
- #define RCU_PLL1_MUL14 CFG1_PLL1MF(12)
- #define RCU_PLL1_MUL15 CFG1_PLL1MF(13)
- #define RCU_PLL1_MUL16 CFG1_PLL1MF(14)
- #define RCU_PLL1_MUL20 CFG1_PLL1MF(15)
- #define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12))
- #define RCU_PLL2_MUL8 CFG1_PLL2MF(6)
- #define RCU_PLL2_MUL9 CFG1_PLL2MF(7)
- #define RCU_PLL2_MUL10 CFG1_PLL2MF(8)
- #define RCU_PLL2_MUL11 CFG1_PLL2MF(9)
- #define RCU_PLL2_MUL12 CFG1_PLL2MF(10)
- #define RCU_PLL2_MUL13 CFG1_PLL2MF(11)
- #define RCU_PLL2_MUL14 CFG1_PLL2MF(12)
- #define RCU_PLL2_MUL15 CFG1_PLL2MF(13)
- #define RCU_PLL2_MUL16 CFG1_PLL2MF(14)
- #define RCU_PLL2_MUL20 CFG1_PLL2MF(15)
- #ifdef GD32F10X_CL
- #define RCU_PREDV0SRC_HXTAL ((uint32_t)0x00000000U)
- #define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL
- #define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U)
- #define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL
- #define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U)
- #define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL
- #endif
- #define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
- #define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0)
- #define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1)
- #define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2)
- #define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3)
- void rcu_deinit(void);
- void rcu_periph_clock_enable(rcu_periph_enum periph);
- void rcu_periph_clock_disable(rcu_periph_enum periph);
- void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph);
- void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph);
- void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset);
- void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset);
- void rcu_bkp_reset_enable(void);
- void rcu_bkp_reset_disable(void);
- void rcu_system_clock_source_config(uint32_t ck_sys);
- uint32_t rcu_system_clock_source_get(void);
- void rcu_ahb_clock_config(uint32_t ck_ahb);
- void rcu_apb1_clock_config(uint32_t ck_apb1);
- void rcu_apb2_clock_config(uint32_t ck_apb2);
- void rcu_ckout0_config(uint32_t ckout0_src);
- void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul);
- #if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
- void rcu_predv0_config(uint32_t predv0_div);
- #elif defined(GD32F10X_CL)
- void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div);
- void rcu_predv1_config(uint32_t predv1_div);
- void rcu_pll1_config(uint32_t pll_mul);
- void rcu_pll2_config(uint32_t pll_mul);
- #endif
- void rcu_adc_clock_config(uint32_t adc_psc);
- void rcu_usb_clock_config(uint32_t usb_psc);
- void rcu_rtc_clock_config(uint32_t rtc_clock_source);
- #ifdef GD32F10X_CL
- void rcu_i2s1_clock_config(uint32_t i2s_clock_source);
- void rcu_i2s2_clock_config(uint32_t i2s_clock_source);
- #endif
- ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci);
- void rcu_osci_on(rcu_osci_type_enum osci);
- void rcu_osci_off(rcu_osci_type_enum osci);
- void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci);
- void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci);
- void rcu_hxtal_clock_monitor_enable(void);
- void rcu_hxtal_clock_monitor_disable(void);
- void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval);
- void rcu_deepsleep_voltage_set(uint32_t dsvol);
- uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock);
- FlagStatus rcu_flag_get(rcu_flag_enum flag);
- void rcu_all_reset_flag_clear(void);
- FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag);
- void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear);
- void rcu_interrupt_enable(rcu_int_enum stab_int);
- void rcu_interrupt_disable(rcu_int_enum stab_int);
- #endif
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