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Lora_gateway...
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lora_gateway.htm

lora_gateway.htm 47 KB
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  1. <!doctype html public "-//w3c//dtd html 4.0 transitional//en">
    2. 

  2. <html><head>
    3. 

  3. <title>Static Call Graph - [..\OBJ\lora_gateway.axf]</title></head>
    4. 

  4. <body><HR>
    5. 

  5. <H1>Static Call Graph for image ..\OBJ\lora_gateway.axf</H1><HR>
    6. 

  6. <BR><P>#&#060CALLGRAPH&#062# ARM Linker, 5060750: Last Updated: Wed Jun 14 08:58:15 2023
    7. 

  7. <BR><P>
    8. 

  8. <H3>Maximum Stack Usage =        132 bytes + Unknown(Cycles, Untraceable Function Pointers)</H3><H3>
    9. 

  9. Call chain for Maximum Stack Depth:</H3>
    10. 

  10. main &rArr; FSMC_SRAM_Init &rArr; SRAM_GPIO_Config &rArr; GPIO_PinAFConfig
    11. 

  11. <P>
    12. 

  12. <H3>
    13. 

  13. Mutually Recursive functions
    14. 

  14. </H3> <LI><a href="#[1c]">ADC_IRQHandler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[1c]">ADC_IRQHandler</a><BR>
    15. 

  15. </UL>
    16. 

  16. <P>
    17. 

  17. <H3>
    18. 

  18. Function Pointers
    19. 

  19. </H3><UL>
    20. 

  20.  <LI><a href="#[1c]">ADC_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    21. 

  21.  <LI><a href="#[4]">BusFault_Handler</a> from stm32f2xx_it.o(i.BusFault_Handler) referenced from startup_stm32f2xx.o(RESET)
    22. 

  22.  <LI><a href="#[1e]">CAN1_RX0_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    23. 

  23.  <LI><a href="#[1f]">CAN1_RX1_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    24. 

  24.  <LI><a href="#[20]">CAN1_SCE_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    25. 

  25.  <LI><a href="#[1d]">CAN1_TX_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    26. 

  26.  <LI><a href="#[4a]">CAN2_RX0_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    27. 

  27.  <LI><a href="#[4b]">CAN2_RX1_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    28. 

  28.  <LI><a href="#[4c]">CAN2_SCE_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    29. 

  29.  <LI><a href="#[49]">CAN2_TX_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    30. 

  30.  <LI><a href="#[59]">CRYP_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    31. 

  31.  <LI><a href="#[58]">DCMI_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    32. 

  32.  <LI><a href="#[15]">DMA1_Stream0_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    33. 

  33.  <LI><a href="#[16]">DMA1_Stream1_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    34. 

  34.  <LI><a href="#[17]">DMA1_Stream2_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    35. 

  35.  <LI><a href="#[18]">DMA1_Stream3_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    36. 

  36.  <LI><a href="#[19]">DMA1_Stream4_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    37. 

  37.  <LI><a href="#[1a]">DMA1_Stream5_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    38. 

  38.  <LI><a href="#[1b]">DMA1_Stream6_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    39. 

  39.  <LI><a href="#[39]">DMA1_Stream7_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    40. 

  40.  <LI><a href="#[42]">DMA2_Stream0_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    41. 

  41.  <LI><a href="#[43]">DMA2_Stream1_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    42. 

  42.  <LI><a href="#[44]">DMA2_Stream2_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    43. 

  43.  <LI><a href="#[45]">DMA2_Stream3_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    44. 

  44.  <LI><a href="#[46]">DMA2_Stream4_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    45. 

  45.  <LI><a href="#[4e]">DMA2_Stream5_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    46. 

  46.  <LI><a href="#[4f]">DMA2_Stream6_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    47. 

  47.  <LI><a href="#[50]">DMA2_Stream7_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    48. 

  48.  <LI><a href="#[7]">DebugMon_Handler</a> from stm32f2xx_it.o(i.DebugMon_Handler) referenced from startup_stm32f2xx.o(RESET)
    49. 

  49.  <LI><a href="#[47]">ETH_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    50. 

  50.  <LI><a href="#[48]">ETH_WKUP_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    51. 

  51.  <LI><a href="#[10]">EXTI0_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    52. 

  52.  <LI><a href="#[32]">EXTI15_10_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    53. 

  53.  <LI><a href="#[11]">EXTI1_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    54. 

  54.  <LI><a href="#[12]">EXTI2_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    55. 

  55.  <LI><a href="#[13]">EXTI3_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    56. 

  56.  <LI><a href="#[14]">EXTI4_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    57. 

  57.  <LI><a href="#[21]">EXTI9_5_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    58. 

  58.  <LI><a href="#[e]">FLASH_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    59. 

  59.  <LI><a href="#[3a]">FSMC_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    60. 

  60.  <LI><a href="#[5a]">HASH_RNG_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    61. 

  61.  <LI><a href="#[2]">HardFault_Handler</a> from stm32f2xx_it.o(i.HardFault_Handler) referenced from startup_stm32f2xx.o(RESET)
    62. 

  62.  <LI><a href="#[2a]">I2C1_ER_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    63. 

  63.  <LI><a href="#[29]">I2C1_EV_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    64. 

  64.  <LI><a href="#[2c]">I2C2_ER_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    65. 

  65.  <LI><a href="#[2b]">I2C2_EV_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    66. 

  66.  <LI><a href="#[53]">I2C3_ER_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    67. 

  67.  <LI><a href="#[52]">I2C3_EV_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    68. 

  68.  <LI><a href="#[3]">MemManage_Handler</a> from stm32f2xx_it.o(i.MemManage_Handler) referenced from startup_stm32f2xx.o(RESET)
    69. 

  69.  <LI><a href="#[1]">NMI_Handler</a> from stm32f2xx_it.o(i.NMI_Handler) referenced from startup_stm32f2xx.o(RESET)
    70. 

  70.  <LI><a href="#[4d]">OTG_FS_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    71. 

  71.  <LI><a href="#[34]">OTG_FS_WKUP_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    72. 

  72.  <LI><a href="#[55]">OTG_HS_EP1_IN_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    73. 

  73.  <LI><a href="#[54]">OTG_HS_EP1_OUT_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    74. 

  74.  <LI><a href="#[57]">OTG_HS_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    75. 

  75.  <LI><a href="#[56]">OTG_HS_WKUP_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    76. 

  76.  <LI><a href="#[b]">PVD_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    77. 

  77.  <LI><a href="#[8]">PendSV_Handler</a> from stm32f2xx_it.o(i.PendSV_Handler) referenced from startup_stm32f2xx.o(RESET)
    78. 

  78.  <LI><a href="#[f]">RCC_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    79. 

  79.  <LI><a href="#[33]">RTC_Alarm_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    80. 

  80.  <LI><a href="#[d]">RTC_WKUP_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    81. 

  81.  <LI><a href="#[0]">Reset_Handler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    82. 

  82.  <LI><a href="#[3b]">SDIO_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    83. 

  83.  <LI><a href="#[2d]">SPI1_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    84. 

  84.  <LI><a href="#[2e]">SPI2_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    85. 

  85.  <LI><a href="#[3d]">SPI3_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    86. 

  86.  <LI><a href="#[6]">SVC_Handler</a> from stm32f2xx_it.o(i.SVC_Handler) referenced from startup_stm32f2xx.o(RESET)
    87. 

  87.  <LI><a href="#[9]">SysTick_Handler</a> from stm32f2xx_it.o(i.SysTick_Handler) referenced from startup_stm32f2xx.o(RESET)
    88. 

  88.  <LI><a href="#[5c]">SystemInit</a> from system_stm32f2xx.o(i.SystemInit) referenced from startup_stm32f2xx.o(.text)
    89. 

  89.  <LI><a href="#[c]">TAMP_STAMP_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    90. 

  90.  <LI><a href="#[22]">TIM1_BRK_TIM9_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    91. 

  91.  <LI><a href="#[25]">TIM1_CC_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    92. 

  92.  <LI><a href="#[24]">TIM1_TRG_COM_TIM11_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    93. 

  93.  <LI><a href="#[23]">TIM1_UP_TIM10_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    94. 

  94.  <LI><a href="#[26]">TIM2_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    95. 

  95.  <LI><a href="#[27]">TIM3_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    96. 

  96.  <LI><a href="#[28]">TIM4_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    97. 

  97.  <LI><a href="#[3c]">TIM5_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    98. 

  98.  <LI><a href="#[40]">TIM6_DAC_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    99. 

  99.  <LI><a href="#[41]">TIM7_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    100. 

  100.  <LI><a href="#[35]">TIM8_BRK_TIM12_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    101. 

  101.  <LI><a href="#[38]">TIM8_CC_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    102. 

  102.  <LI><a href="#[37]">TIM8_TRG_COM_TIM14_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    103. 

  103.  <LI><a href="#[36]">TIM8_UP_TIM13_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    104. 

  104.  <LI><a href="#[3e]">UART4_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    105. 

  105.  <LI><a href="#[3f]">UART5_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    106. 

  106.  <LI><a href="#[2f]">USART1_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    107. 

  107.  <LI><a href="#[30]">USART2_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    108. 

  108.  <LI><a href="#[31]">USART3_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    109. 

  109.  <LI><a href="#[51]">USART6_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    110. 

  110.  <LI><a href="#[5]">UsageFault_Handler</a> from stm32f2xx_it.o(i.UsageFault_Handler) referenced from startup_stm32f2xx.o(RESET)
    111. 

  111.  <LI><a href="#[a]">WWDG_IRQHandler</a> from startup_stm32f2xx.o(.text) referenced from startup_stm32f2xx.o(RESET)
    112. 

  112.  <LI><a href="#[5d]">__main</a> from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f2xx.o(.text)
    113. 

  113.  <LI><a href="#[5e]">fputc</a> from usart.o(i.fputc) referenced from printf8.o(i.__0printf$8)
    114. 

  114.  <LI><a href="#[5b]">main</a> from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
    115. 

  115.  <LI><a href="#[5f]">my_mem_init</a> from malloc.o(i.my_mem_init) referenced from malloc.o(.data)
    116. 

  116.  <LI><a href="#[60]">my_mem_perused</a> from malloc.o(i.my_mem_perused) referenced from malloc.o(.data)
    117. 

  117. </UL>
    118. 

  118. <P>
    119. 

  119. <H3>
    120. 

  120. Global Symbols
    121. 

  121. </H3>
    122. 

  122. <P><STRONG><a name="[5d]"></a>__main</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
    123. 

  123. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(.text)
    124. 

  124. </UL>
    125. 

  125. <P><STRONG><a name="[88]"></a>_main_stk</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
    126. 

  126. 

  127. <P><STRONG><a name="[61]"></a>_main_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
    128. 

  128. <BR><BR>[Calls]<UL><LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
    129. 

  129. </UL>
    130. 

  130. 

  131. <P><STRONG><a name="[66]"></a>__main_after_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
    132. 

  132. <BR><BR>[Called By]<UL><LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
    133. 

  133. </UL>
    134. 

  134. 

  135. <P><STRONG><a name="[89]"></a>_main_clock</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
    136. 

  136. 

  137. <P><STRONG><a name="[8a]"></a>_main_cpp_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
    138. 

  138. 

  139. <P><STRONG><a name="[8b]"></a>_main_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
    140. 

  140. 

  141. <P><STRONG><a name="[8c]"></a>__rt_final_cpp</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D))
    142. 

  142. 

  143. <P><STRONG><a name="[8d]"></a>__rt_final_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F))
    144. 

  144. 

  145. <P><STRONG><a name="[0]"></a>Reset_Handler</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    146. 

  146. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    147. 

  147. </UL>
    148. 

  148. <P><STRONG><a name="[1c]"></a>ADC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    149. 

  149. <BR><BR>[Calls]<UL><LI><a href="#[1c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC_IRQHandler
    150. 

  150. </UL>
    151. 

  151. <BR>[Called By]<UL><LI><a href="#[1c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC_IRQHandler
    152. 

  152. </UL>
    153. 

  153. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    154. 

  154. </UL>
    155. 

  155. <P><STRONG><a name="[1e]"></a>CAN1_RX0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    156. 

  156. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    157. 

  157. </UL>
    158. 

  158. <P><STRONG><a name="[1f]"></a>CAN1_RX1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    159. 

  159. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    160. 

  160. </UL>
    161. 

  161. <P><STRONG><a name="[20]"></a>CAN1_SCE_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    162. 

  162. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    163. 

  163. </UL>
    164. 

  164. <P><STRONG><a name="[1d]"></a>CAN1_TX_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    165. 

  165. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    166. 

  166. </UL>
    167. 

  167. <P><STRONG><a name="[4a]"></a>CAN2_RX0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    168. 

  168. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    169. 

  169. </UL>
    170. 

  170. <P><STRONG><a name="[4b]"></a>CAN2_RX1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    171. 

  171. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    172. 

  172. </UL>
    173. 

  173. <P><STRONG><a name="[4c]"></a>CAN2_SCE_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    174. 

  174. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    175. 

  175. </UL>
    176. 

  176. <P><STRONG><a name="[49]"></a>CAN2_TX_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    177. 

  177. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    178. 

  178. </UL>
    179. 

  179. <P><STRONG><a name="[59]"></a>CRYP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    180. 

  180. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    181. 

  181. </UL>
    182. 

  182. <P><STRONG><a name="[58]"></a>DCMI_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    183. 

  183. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    184. 

  184. </UL>
    185. 

  185. <P><STRONG><a name="[15]"></a>DMA1_Stream0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    186. 

  186. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    187. 

  187. </UL>
    188. 

  188. <P><STRONG><a name="[16]"></a>DMA1_Stream1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    189. 

  189. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    190. 

  190. </UL>
    191. 

  191. <P><STRONG><a name="[17]"></a>DMA1_Stream2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    192. 

  192. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    193. 

  193. </UL>
    194. 

  194. <P><STRONG><a name="[18]"></a>DMA1_Stream3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    195. 

  195. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    196. 

  196. </UL>
    197. 

  197. <P><STRONG><a name="[19]"></a>DMA1_Stream4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    198. 

  198. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    199. 

  199. </UL>
    200. 

  200. <P><STRONG><a name="[1a]"></a>DMA1_Stream5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    201. 

  201. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    202. 

  202. </UL>
    203. 

  203. <P><STRONG><a name="[1b]"></a>DMA1_Stream6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    204. 

  204. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    205. 

  205. </UL>
    206. 

  206. <P><STRONG><a name="[39]"></a>DMA1_Stream7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    207. 

  207. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    208. 

  208. </UL>
    209. 

  209. <P><STRONG><a name="[42]"></a>DMA2_Stream0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    210. 

  210. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    211. 

  211. </UL>
    212. 

  212. <P><STRONG><a name="[43]"></a>DMA2_Stream1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    213. 

  213. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    214. 

  214. </UL>
    215. 

  215. <P><STRONG><a name="[44]"></a>DMA2_Stream2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    216. 

  216. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    217. 

  217. </UL>
    218. 

  218. <P><STRONG><a name="[45]"></a>DMA2_Stream3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    219. 

  219. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    220. 

  220. </UL>
    221. 

  221. <P><STRONG><a name="[46]"></a>DMA2_Stream4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    222. 

  222. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    223. 

  223. </UL>
    224. 

  224. <P><STRONG><a name="[4e]"></a>DMA2_Stream5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    225. 

  225. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    226. 

  226. </UL>
    227. 

  227. <P><STRONG><a name="[4f]"></a>DMA2_Stream6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    228. 

  228. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    229. 

  229. </UL>
    230. 

  230. <P><STRONG><a name="[50]"></a>DMA2_Stream7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    231. 

  231. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    232. 

  232. </UL>
    233. 

  233. <P><STRONG><a name="[47]"></a>ETH_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    234. 

  234. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    235. 

  235. </UL>
    236. 

  236. <P><STRONG><a name="[48]"></a>ETH_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    237. 

  237. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    238. 

  238. </UL>
    239. 

  239. <P><STRONG><a name="[10]"></a>EXTI0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    240. 

  240. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    241. 

  241. </UL>
    242. 

  242. <P><STRONG><a name="[32]"></a>EXTI15_10_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    243. 

  243. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    244. 

  244. </UL>
    245. 

  245. <P><STRONG><a name="[11]"></a>EXTI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    246. 

  246. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    247. 

  247. </UL>
    248. 

  248. <P><STRONG><a name="[12]"></a>EXTI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    249. 

  249. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    250. 

  250. </UL>
    251. 

  251. <P><STRONG><a name="[13]"></a>EXTI3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    252. 

  252. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    253. 

  253. </UL>
    254. 

  254. <P><STRONG><a name="[14]"></a>EXTI4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    255. 

  255. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    256. 

  256. </UL>
    257. 

  257. <P><STRONG><a name="[21]"></a>EXTI9_5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    258. 

  258. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    259. 

  259. </UL>
    260. 

  260. <P><STRONG><a name="[e]"></a>FLASH_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    261. 

  261. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    262. 

  262. </UL>
    263. 

  263. <P><STRONG><a name="[3a]"></a>FSMC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    264. 

  264. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    265. 

  265. </UL>
    266. 

  266. <P><STRONG><a name="[5a]"></a>HASH_RNG_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    267. 

  267. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    268. 

  268. </UL>
    269. 

  269. <P><STRONG><a name="[2a]"></a>I2C1_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    270. 

  270. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    271. 

  271. </UL>
    272. 

  272. <P><STRONG><a name="[29]"></a>I2C1_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    273. 

  273. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    274. 

  274. </UL>
    275. 

  275. <P><STRONG><a name="[2c]"></a>I2C2_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    276. 

  276. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    277. 

  277. </UL>
    278. 

  278. <P><STRONG><a name="[2b]"></a>I2C2_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    279. 

  279. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    280. 

  280. </UL>
    281. 

  281. <P><STRONG><a name="[53]"></a>I2C3_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    282. 

  282. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    283. 

  283. </UL>
    284. 

  284. <P><STRONG><a name="[52]"></a>I2C3_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    285. 

  285. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    286. 

  286. </UL>
    287. 

  287. <P><STRONG><a name="[4d]"></a>OTG_FS_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    288. 

  288. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    289. 

  289. </UL>
    290. 

  290. <P><STRONG><a name="[34]"></a>OTG_FS_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    291. 

  291. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    292. 

  292. </UL>
    293. 

  293. <P><STRONG><a name="[55]"></a>OTG_HS_EP1_IN_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    294. 

  294. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    295. 

  295. </UL>
    296. 

  296. <P><STRONG><a name="[54]"></a>OTG_HS_EP1_OUT_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    297. 

  297. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    298. 

  298. </UL>
    299. 

  299. <P><STRONG><a name="[57]"></a>OTG_HS_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    300. 

  300. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    301. 

  301. </UL>
    302. 

  302. <P><STRONG><a name="[56]"></a>OTG_HS_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    303. 

  303. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    304. 

  304. </UL>
    305. 

  305. <P><STRONG><a name="[b]"></a>PVD_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    306. 

  306. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    307. 

  307. </UL>
    308. 

  308. <P><STRONG><a name="[f]"></a>RCC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    309. 

  309. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    310. 

  310. </UL>
    311. 

  311. <P><STRONG><a name="[33]"></a>RTC_Alarm_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    312. 

  312. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    313. 

  313. </UL>
    314. 

  314. <P><STRONG><a name="[d]"></a>RTC_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    315. 

  315. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    316. 

  316. </UL>
    317. 

  317. <P><STRONG><a name="[3b]"></a>SDIO_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    318. 

  318. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    319. 

  319. </UL>
    320. 

  320. <P><STRONG><a name="[2d]"></a>SPI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    321. 

  321. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    322. 

  322. </UL>
    323. 

  323. <P><STRONG><a name="[2e]"></a>SPI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    324. 

  324. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    325. 

  325. </UL>
    326. 

  326. <P><STRONG><a name="[3d]"></a>SPI3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    327. 

  327. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    328. 

  328. </UL>
    329. 

  329. <P><STRONG><a name="[c]"></a>TAMP_STAMP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    330. 

  330. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    331. 

  331. </UL>
    332. 

  332. <P><STRONG><a name="[22]"></a>TIM1_BRK_TIM9_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    333. 

  333. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    334. 

  334. </UL>
    335. 

  335. <P><STRONG><a name="[25]"></a>TIM1_CC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    336. 

  336. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    337. 

  337. </UL>
    338. 

  338. <P><STRONG><a name="[24]"></a>TIM1_TRG_COM_TIM11_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    339. 

  339. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    340. 

  340. </UL>
    341. 

  341. <P><STRONG><a name="[23]"></a>TIM1_UP_TIM10_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    342. 

  342. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    343. 

  343. </UL>
    344. 

  344. <P><STRONG><a name="[26]"></a>TIM2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    345. 

  345. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    346. 

  346. </UL>
    347. 

  347. <P><STRONG><a name="[27]"></a>TIM3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    348. 

  348. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    349. 

  349. </UL>
    350. 

  350. <P><STRONG><a name="[28]"></a>TIM4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    351. 

  351. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    352. 

  352. </UL>
    353. 

  353. <P><STRONG><a name="[3c]"></a>TIM5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    354. 

  354. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    355. 

  355. </UL>
    356. 

  356. <P><STRONG><a name="[40]"></a>TIM6_DAC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    357. 

  357. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    358. 

  358. </UL>
    359. 

  359. <P><STRONG><a name="[41]"></a>TIM7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    360. 

  360. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    361. 

  361. </UL>
    362. 

  362. <P><STRONG><a name="[35]"></a>TIM8_BRK_TIM12_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    363. 

  363. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    364. 

  364. </UL>
    365. 

  365. <P><STRONG><a name="[38]"></a>TIM8_CC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    366. 

  366. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    367. 

  367. </UL>
    368. 

  368. <P><STRONG><a name="[37]"></a>TIM8_TRG_COM_TIM14_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    369. 

  369. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    370. 

  370. </UL>
    371. 

  371. <P><STRONG><a name="[36]"></a>TIM8_UP_TIM13_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    372. 

  372. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    373. 

  373. </UL>
    374. 

  374. <P><STRONG><a name="[3e]"></a>UART4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    375. 

  375. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    376. 

  376. </UL>
    377. 

  377. <P><STRONG><a name="[3f]"></a>UART5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    378. 

  378. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    379. 

  379. </UL>
    380. 

  380. <P><STRONG><a name="[2f]"></a>USART1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    381. 

  381. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    382. 

  382. </UL>
    383. 

  383. <P><STRONG><a name="[30]"></a>USART2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    384. 

  384. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    385. 

  385. </UL>
    386. 

  386. <P><STRONG><a name="[31]"></a>USART3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    387. 

  387. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    388. 

  388. </UL>
    389. 

  389. <P><STRONG><a name="[51]"></a>USART6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    390. 

  390. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    391. 

  391. </UL>
    392. 

  392. <P><STRONG><a name="[a]"></a>WWDG_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f2xx.o(.text))
    393. 

  393. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    394. 

  394. </UL>
    395. 

  395. <P><STRONG><a name="[63]"></a>__aeabi_uldivmod</STRONG> (Thumb, 98 bytes, Stack size 40 bytes, uldiv.o(.text), UNUSED)
    396. 

  396. <BR><BR>[Calls]<UL><LI><a href="#[64]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_llsr
    397. 

  397. <LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_llsl
    398. 

  398. </UL>
    399. 

  399. <BR>[Called By]<UL><LI><a href="#[82]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_core
    400. 

  400. </UL>
    401. 

  401. 

  402. <P><STRONG><a name="[65]"></a>__aeabi_llsl</STRONG> (Thumb, 30 bytes, Stack size 0 bytes, llshl.o(.text), UNUSED)
    403. 

  403. <BR><BR>[Called By]<UL><LI><a href="#[63]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_uldivmod
    404. 

  404. </UL>
    405. 

  405. 

  406. <P><STRONG><a name="[8e]"></a>_ll_shift_l</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, llshl.o(.text), UNUSED)
    407. 

  407. 

  408. <P><STRONG><a name="[64]"></a>__aeabi_llsr</STRONG> (Thumb, 32 bytes, Stack size 0 bytes, llushr.o(.text), UNUSED)
    409. 

  409. <BR><BR>[Called By]<UL><LI><a href="#[63]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_uldivmod
    410. 

  410. </UL>
    411. 

  411. 

  412. <P><STRONG><a name="[8f]"></a>_ll_ushift_r</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, llushr.o(.text), UNUSED)
    413. 

  413. 

  414. <P><STRONG><a name="[62]"></a>__scatterload</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
    415. 

  415. <BR><BR>[Calls]<UL><LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__main_after_scatterload
    416. 

  416. </UL>
    417. 

  417. <BR>[Called By]<UL><LI><a href="#[61]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_main_scatterload
    418. 

  418. </UL>
    419. 

  419. 

  420. <P><STRONG><a name="[90]"></a>__scatterload_rt2</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
    421. 

  421. 

  422. <P><STRONG><a name="[4]"></a>BusFault_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, stm32f2xx_it.o(i.BusFault_Handler))
    423. 

  423. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    424. 

  424. </UL>
    425. 

  425. <P><STRONG><a name="[7]"></a>DebugMon_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, stm32f2xx_it.o(i.DebugMon_Handler))
    426. 

  426. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    427. 

  427. </UL>
    428. 

  428. <P><STRONG><a name="[67]"></a>Debug_USART_Config</STRONG> (Thumb, 128 bytes, Stack size 32 bytes, usart.o(i.Debug_USART_Config))
    429. 

  429. <BR><BR>[Stack]<UL><LI>Max Depth = 100<LI>Call Chain = Debug_USART_Config &rArr; USART_Init &rArr; RCC_GetClocksFreq
    430. 

  430. </UL>
    431. 

  431. <BR>[Calls]<UL><LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_PinAFConfig
    432. 

  432. <LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_Init
    433. 

  433. <LI><a href="#[6c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;USART_Init
    434. 

  434. <LI><a href="#[6d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;USART_Cmd
    435. 

  435. <LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;RCC_APB2PeriphClockCmd
    436. 

  436. <LI><a href="#[69]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;RCC_AHB1PeriphClockCmd
    437. 

  437. </UL>
    438. 

  438. <BR>[Called By]<UL><LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
    439. 

  439. </UL>
    440. 

  440. 

  441. <P><STRONG><a name="[73]"></a>FSMC_NANDCmd</STRONG> (Thumb, 82 bytes, Stack size 0 bytes, stm32f2xx_fsmc.o(i.FSMC_NANDCmd))
    442. 

  442. <BR><BR>[Called By]<UL><LI><a href="#[70]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NAND_Init
    443. 

  443. </UL>
    444. 

  444. 

  445. <P><STRONG><a name="[72]"></a>FSMC_NANDInit</STRONG> (Thumb, 132 bytes, Stack size 12 bytes, stm32f2xx_fsmc.o(i.FSMC_NANDInit))
    446. 

  446. <BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = FSMC_NANDInit
    447. 

  447. </UL>
    448. 

  448. <BR>[Called By]<UL><LI><a href="#[70]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NAND_Init
    449. 

  449. </UL>
    450. 

  450. 

  451. <P><STRONG><a name="[7c]"></a>FSMC_NORSRAMCmd</STRONG> (Thumb, 46 bytes, Stack size 0 bytes, stm32f2xx_fsmc.o(i.FSMC_NORSRAMCmd))
    452. 

  452. <BR><BR>[Called By]<UL><LI><a href="#[79]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_SRAM_Init
    453. 

  453. </UL>
    454. 

  454. 

  455. <P><STRONG><a name="[7b]"></a>FSMC_NORSRAMInit</STRONG> (Thumb, 230 bytes, Stack size 0 bytes, stm32f2xx_fsmc.o(i.FSMC_NORSRAMInit))
    456. 

  456. <BR><BR>[Called By]<UL><LI><a href="#[79]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_SRAM_Init
    457. 

  457. </UL>
    458. 

  458. 

  459. <P><STRONG><a name="[79]"></a>FSMC_SRAM_Init</STRONG> (Thumb, 106 bytes, Stack size 96 bytes, sram.o(i.FSMC_SRAM_Init))
    460. 

  460. <BR><BR>[Stack]<UL><LI>Max Depth = 132<LI>Call Chain = FSMC_SRAM_Init &rArr; SRAM_GPIO_Config &rArr; GPIO_PinAFConfig
    461. 

  461. </UL>
    462. 

  462. <BR>[Calls]<UL><LI><a href="#[7b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NORSRAMInit
    463. 

  463. <LI><a href="#[7c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NORSRAMCmd
    464. 

  464. <LI><a href="#[71]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;RCC_AHB3PeriphClockCmd
    465. 

  465. <LI><a href="#[7a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SRAM_GPIO_Config
    466. 

  466. </UL>
    467. 

  467. <BR>[Called By]<UL><LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
    468. 

  468. </UL>
    469. 

  469. 

  470. <P><STRONG><a name="[6a]"></a>GPIO_Init</STRONG> (Thumb, 144 bytes, Stack size 20 bytes, stm32f2xx_gpio.o(i.GPIO_Init))
    471. 

  471. <BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = GPIO_Init
    472. 

  472. </UL>
    473. 

  473. <BR>[Called By]<UL><LI><a href="#[67]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Debug_USART_Config
    474. 

  474. <LI><a href="#[70]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NAND_Init
    475. 

  475. <LI><a href="#[7a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SRAM_GPIO_Config
    476. 

  476. </UL>
    477. 

  477. 

  478. <P><STRONG><a name="[6b]"></a>GPIO_PinAFConfig</STRONG> (Thumb, 70 bytes, Stack size 20 bytes, stm32f2xx_gpio.o(i.GPIO_PinAFConfig))
    479. 

  479. <BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = GPIO_PinAFConfig
    480. 

  480. </UL>
    481. 

  481. <BR>[Called By]<UL><LI><a href="#[67]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Debug_USART_Config
    482. 

  482. <LI><a href="#[70]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NAND_Init
    483. 

  483. <LI><a href="#[7a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SRAM_GPIO_Config
    484. 

  484. </UL>
    485. 

  485. 

  486. <P><STRONG><a name="[75]"></a>GPIO_ReadInputDataBit</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, stm32f2xx_gpio.o(i.GPIO_ReadInputDataBit))
    487. 

  487. <BR><BR>[Called By]<UL><LI><a href="#[74]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NAND_ReadPage
    488. 

  488. </UL>
    489. 

  489. 

  490. <P><STRONG><a name="[2]"></a>HardFault_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, stm32f2xx_it.o(i.HardFault_Handler))
    491. 

  491. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    492. 

  492. </UL>
    493. 

  493. <P><STRONG><a name="[3]"></a>MemManage_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, stm32f2xx_it.o(i.MemManage_Handler))
    494. 

  494. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    495. 

  495. </UL>
    496. 

  496. <P><STRONG><a name="[7e]"></a>NAND_Init</STRONG> (Thumb, 20 bytes, Stack size 8 bytes, nandflash.o(i.NAND_Init))
    497. 

  497. <BR><BR>[Stack]<UL><LI>Max Depth = 92<LI>Call Chain = NAND_Init &rArr; FSMC_NAND_Init &rArr; GPIO_PinAFConfig
    498. 

  498. </UL>
    499. 

  499. <BR>[Calls]<UL><LI><a href="#[7d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NAND_BuildLUT
    500. 

  500. <LI><a href="#[78]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NAND_Reset
    501. 

  501. <LI><a href="#[70]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NAND_Init
    502. 

  502. </UL>
    503. 

  503. <BR>[Called By]<UL><LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
    504. 

  504. </UL>
    505. 

  505. 

  506. <P><STRONG><a name="[1]"></a>NMI_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, stm32f2xx_it.o(i.NMI_Handler))
    507. 

  507. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    508. 

  508. </UL>
    509. 

  509. <P><STRONG><a name="[8]"></a>PendSV_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, stm32f2xx_it.o(i.PendSV_Handler))
    510. 

  510. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    511. 

  511. </UL>
    512. 

  512. <P><STRONG><a name="[69]"></a>RCC_AHB1PeriphClockCmd</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, stm32f2xx_rcc.o(i.RCC_AHB1PeriphClockCmd))
    513. 

  513. <BR><BR>[Called By]<UL><LI><a href="#[67]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Debug_USART_Config
    514. 

  514. <LI><a href="#[70]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NAND_Init
    515. 

  515. <LI><a href="#[7a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SRAM_GPIO_Config
    516. 

  516. </UL>
    517. 

  517. 

  518. <P><STRONG><a name="[71]"></a>RCC_AHB3PeriphClockCmd</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, stm32f2xx_rcc.o(i.RCC_AHB3PeriphClockCmd))
    519. 

  519. <BR><BR>[Called By]<UL><LI><a href="#[79]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_SRAM_Init
    520. 

  520. <LI><a href="#[70]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NAND_Init
    521. 

  521. </UL>
    522. 

  522. 

  523. <P><STRONG><a name="[68]"></a>RCC_APB2PeriphClockCmd</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, stm32f2xx_rcc.o(i.RCC_APB2PeriphClockCmd))
    524. 

  524. <BR><BR>[Called By]<UL><LI><a href="#[67]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Debug_USART_Config
    525. 

  525. </UL>
    526. 

  526. 

  527. <P><STRONG><a name="[80]"></a>RCC_GetClocksFreq</STRONG> (Thumb, 214 bytes, Stack size 20 bytes, stm32f2xx_rcc.o(i.RCC_GetClocksFreq))
    528. 

  528. <BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = RCC_GetClocksFreq
    529. 

  529. </UL>
    530. 

  530. <BR>[Called By]<UL><LI><a href="#[6c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;USART_Init
    531. 

  531. </UL>
    532. 

  532. 

  533. <P><STRONG><a name="[6]"></a>SVC_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, stm32f2xx_it.o(i.SVC_Handler))
    534. 

  534. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    535. 

  535. </UL>
    536. 

  536. <P><STRONG><a name="[9]"></a>SysTick_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, stm32f2xx_it.o(i.SysTick_Handler))
    537. 

  537. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    538. 

  538. </UL>
    539. 

  539. <P><STRONG><a name="[5c]"></a>SystemInit</STRONG> (Thumb, 74 bytes, Stack size 8 bytes, system_stm32f2xx.o(i.SystemInit))
    540. 

  540. <BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = SystemInit &rArr; SetSysClock
    541. 

  541. </UL>
    542. 

  542. <BR>[Calls]<UL><LI><a href="#[7f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SetSysClock
    543. 

  543. </UL>
    544. 

  544. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(.text)
    545. 

  545. </UL>
    546. 

  546. <P><STRONG><a name="[6d]"></a>USART_Cmd</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, stm32f2xx_usart.o(i.USART_Cmd))
    547. 

  547. <BR><BR>[Called By]<UL><LI><a href="#[67]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Debug_USART_Config
    548. 

  548. </UL>
    549. 

  549. 

  550. <P><STRONG><a name="[86]"></a>USART_GetFlagStatus</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, stm32f2xx_usart.o(i.USART_GetFlagStatus))
    551. 

  551. <BR><BR>[Called By]<UL><LI><a href="#[5e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fputc
    552. 

  552. </UL>
    553. 

  553. 

  554. <P><STRONG><a name="[6c]"></a>USART_Init</STRONG> (Thumb, 204 bytes, Stack size 48 bytes, stm32f2xx_usart.o(i.USART_Init))
    555. 

  555. <BR><BR>[Stack]<UL><LI>Max Depth = 68<LI>Call Chain = USART_Init &rArr; RCC_GetClocksFreq
    556. 

  556. </UL>
    557. 

  557. <BR>[Calls]<UL><LI><a href="#[80]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;RCC_GetClocksFreq
    558. 

  558. </UL>
    559. 

  559. <BR>[Called By]<UL><LI><a href="#[67]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Debug_USART_Config
    560. 

  560. </UL>
    561. 

  561. 

  562. <P><STRONG><a name="[85]"></a>USART_SendData</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, stm32f2xx_usart.o(i.USART_SendData))
    563. 

  563. <BR><BR>[Called By]<UL><LI><a href="#[5e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fputc
    564. 

  564. </UL>
    565. 

  565. 

  566. <P><STRONG><a name="[5]"></a>UsageFault_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, stm32f2xx_it.o(i.UsageFault_Handler))
    567. 

  567. <BR>[Address Reference Count : 1]<UL><LI> startup_stm32f2xx.o(RESET)
    568. 

  568. </UL>
    569. 

  569. <P><STRONG><a name="[81]"></a>__0printf$8</STRONG> (Thumb, 22 bytes, Stack size 24 bytes, printf8.o(i.__0printf$8), UNUSED)
    570. 

  570. <BR><BR>[Calls]<UL><LI><a href="#[82]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_core
    571. 

  571. </UL>
    572. 

  572. 

  573. <P><STRONG><a name="[91]"></a>__1printf$8</STRONG> (Thumb, 0 bytes, Stack size 24 bytes, printf8.o(i.__0printf$8), UNUSED)
    574. 

  574. 

  575. <P><STRONG><a name="[77]"></a>__2printf</STRONG> (Thumb, 0 bytes, Stack size 24 bytes, printf8.o(i.__0printf$8))
    576. 

  576. <BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = __2printf
    577. 

  577. </UL>
    578. 

  578. <BR>[Called By]<UL><LI><a href="#[76]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NAND_ReadSpare
    579. 

  579. </UL>
    580. 

  580. 

  581. <P><STRONG><a name="[92]"></a>__scatterload_copy</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
    582. 

  582. 

  583. <P><STRONG><a name="[93]"></a>__scatterload_null</STRONG> (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
    584. 

  584. 

  585. <P><STRONG><a name="[94]"></a>__scatterload_zeroinit</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
    586. 

  586. 

  587. <P><STRONG><a name="[5e]"></a>fputc</STRONG> (Thumb, 32 bytes, Stack size 16 bytes, usart.o(i.fputc))
    588. 

  588. <BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = fputc
    589. 

  589. </UL>
    590. 

  590. <BR>[Calls]<UL><LI><a href="#[85]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;USART_SendData
    591. 

  591. <LI><a href="#[86]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;USART_GetFlagStatus
    592. 

  592. </UL>
    593. 

  593. <BR>[Address Reference Count : 1]<UL><LI> printf8.o(i.__0printf$8)
    594. 

  594. </UL>
    595. 

  595. <P><STRONG><a name="[5b]"></a>main</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, main.o(i.main))
    596. 

  596. <BR><BR>[Stack]<UL><LI>Max Depth = 132<LI>Call Chain = main &rArr; FSMC_SRAM_Init &rArr; SRAM_GPIO_Config &rArr; GPIO_PinAFConfig
    597. 

  597. </UL>
    598. 

  598. <BR>[Calls]<UL><LI><a href="#[5f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;my_mem_init
    599. 

  599. <LI><a href="#[7e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NAND_Init
    600. 

  600. <LI><a href="#[79]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_SRAM_Init
    601. 

  601. <LI><a href="#[67]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Debug_USART_Config
    602. 

  602. </UL>
    603. 

  603. <BR>[Address Reference Count : 1]<UL><LI> entry9a.o(.ARM.Collect$$$$0000000B)
    604. 

  604. </UL>
    605. 

  605. <P><STRONG><a name="[5f]"></a>my_mem_init</STRONG> (Thumb, 54 bytes, Stack size 8 bytes, malloc.o(i.my_mem_init))
    606. 

  606. <BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = my_mem_init &rArr; mymemset
    607. 

  607. </UL>
    608. 

  608. <BR>[Calls]<UL><LI><a href="#[87]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;mymemset
    609. 

  609. </UL>
    610. 

  610. <BR>[Called By]<UL><LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
    611. 

  611. </UL>
    612. 

  612. <BR>[Address Reference Count : 1]<UL><LI> malloc.o(.data)
    613. 

  613. </UL>
    614. 

  614. <P><STRONG><a name="[60]"></a>my_mem_perused</STRONG> (Thumb, 54 bytes, Stack size 8 bytes, malloc.o(i.my_mem_perused))
    615. 

  615. <BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = my_mem_perused
    616. 

  616. </UL>
    617. 

  617. <BR>[Address Reference Count : 1]<UL><LI> malloc.o(.data)
    618. 

  618. </UL>
    619. 

  619. <P><STRONG><a name="[87]"></a>mymemset</STRONG> (Thumb, 20 bytes, Stack size 12 bytes, malloc.o(i.mymemset))
    620. 

  620. <BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = mymemset
    621. 

  621. </UL>
    622. 

  622. <BR>[Called By]<UL><LI><a href="#[5f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;my_mem_init
    623. 

  623. </UL>
    624. 

  624. <P>
    625. 

  625. <H3>
    626. 

  626. Local Symbols
    627. 

  627. </H3>
    628. 

  628. <P><STRONG><a name="[7f]"></a>SetSysClock</STRONG> (Thumb, 192 bytes, Stack size 12 bytes, system_stm32f2xx.o(i.SetSysClock))
    629. 

  629. <BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = SetSysClock
    630. 

  630. </UL>
    631. 

  631. <BR>[Called By]<UL><LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemInit
    632. 

  632. </UL>
    633. 

  633. 

  634. <P><STRONG><a name="[7a]"></a>SRAM_GPIO_Config</STRONG> (Thumb, 956 bytes, Stack size 16 bytes, sram.o(i.SRAM_GPIO_Config))
    635. 

  635. <BR><BR>[Stack]<UL><LI>Max Depth = 36<LI>Call Chain = SRAM_GPIO_Config &rArr; GPIO_PinAFConfig
    636. 

  636. </UL>
    637. 

  637. <BR>[Calls]<UL><LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_PinAFConfig
    638. 

  638. <LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_Init
    639. 

  639. <LI><a href="#[69]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;RCC_AHB1PeriphClockCmd
    640. 

  640. </UL>
    641. 

  641. <BR>[Called By]<UL><LI><a href="#[79]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_SRAM_Init
    642. 

  642. </UL>
    643. 

  643. 

  644. <P><STRONG><a name="[6e]"></a>FSMC_NAND_GetStatus</STRONG> (Thumb, 40 bytes, Stack size 16 bytes, nandflash.o(i.FSMC_NAND_GetStatus))
    645. 

  645. <BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = FSMC_NAND_GetStatus
    646. 

  646. </UL>
    647. 

  647. <BR>[Calls]<UL><LI><a href="#[6f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NAND_ReadStatus
    648. 

  648. </UL>
    649. 

  649. <BR>[Called By]<UL><LI><a href="#[78]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NAND_Reset
    650. 

  650. </UL>
    651. 

  651. 

  652. <P><STRONG><a name="[70]"></a>FSMC_NAND_Init</STRONG> (Thumb, 280 bytes, Stack size 64 bytes, nandflash.o(i.FSMC_NAND_Init))
    653. 

  653. <BR><BR>[Stack]<UL><LI>Max Depth = 84<LI>Call Chain = FSMC_NAND_Init &rArr; GPIO_PinAFConfig
    654. 

  654. </UL>
    655. 

  655. <BR>[Calls]<UL><LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_PinAFConfig
    656. 

  656. <LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_Init
    657. 

  657. <LI><a href="#[72]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NANDInit
    658. 

  658. <LI><a href="#[73]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NANDCmd
    659. 

  659. <LI><a href="#[71]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;RCC_AHB3PeriphClockCmd
    660. 

  660. <LI><a href="#[69]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;RCC_AHB1PeriphClockCmd
    661. 

  661. </UL>
    662. 

  662. <BR>[Called By]<UL><LI><a href="#[7e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NAND_Init
    663. 

  663. </UL>
    664. 

  664. 

  665. <P><STRONG><a name="[74]"></a>FSMC_NAND_ReadPage</STRONG> (Thumb, 94 bytes, Stack size 24 bytes, nandflash.o(i.FSMC_NAND_ReadPage))
    666. 

  666. <BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = FSMC_NAND_ReadPage
    667. 

  667. </UL>
    668. 

  668. <BR>[Calls]<UL><LI><a href="#[75]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_ReadInputDataBit
    669. 

  669. </UL>
    670. 

  670. <BR>[Called By]<UL><LI><a href="#[76]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NAND_ReadSpare
    671. 

  671. </UL>
    672. 

  672. 

  673. <P><STRONG><a name="[76]"></a>FSMC_NAND_ReadSpare</STRONG> (Thumb, 48 bytes, Stack size 24 bytes, nandflash.o(i.FSMC_NAND_ReadSpare))
    674. 

  674. <BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = FSMC_NAND_ReadSpare &rArr; FSMC_NAND_ReadPage
    675. 

  675. </UL>
    676. 

  676. <BR>[Calls]<UL><LI><a href="#[74]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NAND_ReadPage
    677. 

  677. <LI><a href="#[77]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__2printf
    678. 

  678. </UL>
    679. 

  679. <BR>[Called By]<UL><LI><a href="#[7d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NAND_BuildLUT
    680. 

  680. </UL>
    681. 

  681. 

  682. <P><STRONG><a name="[6f]"></a>FSMC_NAND_ReadStatus</STRONG> (Thumb, 38 bytes, Stack size 0 bytes, nandflash.o(i.FSMC_NAND_ReadStatus))
    683. 

  683. <BR><BR>[Called By]<UL><LI><a href="#[6e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NAND_GetStatus
    684. 

  684. </UL>
    685. 

  685. 

  686. <P><STRONG><a name="[78]"></a>FSMC_NAND_Reset</STRONG> (Thumb, 24 bytes, Stack size 8 bytes, nandflash.o(i.FSMC_NAND_Reset))
    687. 

  687. <BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = FSMC_NAND_Reset &rArr; FSMC_NAND_GetStatus
    688. 

  688. </UL>
    689. 

  689. <BR>[Calls]<UL><LI><a href="#[6e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NAND_GetStatus
    690. 

  690. </UL>
    691. 

  691. <BR>[Called By]<UL><LI><a href="#[7e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NAND_Init
    692. 

  692. </UL>
    693. 

  693. 

  694. <P><STRONG><a name="[7d]"></a>NAND_BuildLUT</STRONG> (Thumb, 186 bytes, Stack size 16 bytes, nandflash.o(i.NAND_BuildLUT))
    695. 

  695. <BR><BR>[Stack]<UL><LI>Max Depth = 64<LI>Call Chain = NAND_BuildLUT &rArr; FSMC_NAND_ReadSpare &rArr; FSMC_NAND_ReadPage
    696. 

  696. </UL>
    697. 

  697. <BR>[Calls]<UL><LI><a href="#[76]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;FSMC_NAND_ReadSpare
    698. 

  698. </UL>
    699. 

  699. <BR>[Called By]<UL><LI><a href="#[7e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NAND_Init
    700. 

  700. </UL>
    701. 

  701. 

  702. <P><STRONG><a name="[82]"></a>_printf_core</STRONG> (Thumb, 996 bytes, Stack size 104 bytes, printf8.o(i._printf_core), UNUSED)
    703. 

  703. <BR><BR>[Calls]<UL><LI><a href="#[83]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_pre_padding
    704. 

  704. <LI><a href="#[84]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_post_padding
    705. 

  705. <LI><a href="#[63]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_uldivmod
    706. 

  706. </UL>
    707. 

  707. <BR>[Called By]<UL><LI><a href="#[81]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__0printf$8
    708. 

  708. </UL>
    709. 

  709. 

  710. <P><STRONG><a name="[84]"></a>_printf_post_padding</STRONG> (Thumb, 36 bytes, Stack size 24 bytes, printf8.o(i._printf_post_padding), UNUSED)
    711. 

  711. <BR><BR>[Called By]<UL><LI><a href="#[82]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_core
    712. 

  712. </UL>
    713. 

  713. 

  714. <P><STRONG><a name="[83]"></a>_printf_pre_padding</STRONG> (Thumb, 46 bytes, Stack size 24 bytes, printf8.o(i._printf_pre_padding), UNUSED)
    715. 

  715. <BR><BR>[Called By]<UL><LI><a href="#[82]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_core
    716. 

  716. </UL>
    717. 

  717. <P>
    718. 

  718. <H3>
    719. 

  719. Undefined Global Symbols
    720. 

  720. </H3><HR></body></html>
    721.