Business-code/fpga/fpga_pwm_trace_project/rtl/limit_trace_capture.v

`timescale 1ns/1ps

// -----------------------------------------------------------------------------
// limit_trace_capture
//
// Synchronizes the three raw limit-switch trace inputs and remembers whether a
// rising/falling transition occurred since the last accepted report snapshot.
// The trace firmware reports RAW electrical logic levels; it does not assume
// whether the machine's limit switch is active-high or active-low.
// -----------------------------------------------------------------------------
module limit_trace_capture (
    input  wire       clk,
    input  wire       reset_n,
    input  wire [2:0] limit_in,
    input  wire       clear_seen,

    output wire [2:0] level,
    output reg  [2:0] rise_seen,
    output reg  [2:0] fall_seen
);

    reg [2:0] limit_meta;
    reg [2:0] limit_sync;
    reg [2:0] limit_sync_d;

    wire [2:0] rise_edge =  limit_sync & ~limit_sync_d;
    wire [2:0] fall_edge = ~limit_sync &  limit_sync_d;

    assign level = limit_sync;

    always @(posedge clk or negedge reset_n) begin
        if (!reset_n) begin
            limit_meta   <= 3'b000;
            limit_sync   <= 3'b000;
            limit_sync_d <= 3'b000;
        end else begin
            limit_meta   <= limit_in;
            limit_sync   <= limit_meta;
            limit_sync_d <= limit_sync;
        end
    end

    always @(posedge clk or negedge reset_n) begin
        if (!reset_n) begin
            rise_seen <= 3'b000;
            fall_seen <= 3'b000;
        end else if (clear_seen) begin
            // If an edge occurs in the exact clear cycle, retain it for the
            // following snapshot instead of losing it.
            rise_seen <= rise_edge;
            fall_seen <= fall_edge;
        end else begin
            rise_seen <= rise_seen | rise_edge;
            fall_seen <= fall_seen | fall_edge;
        end
    end

endmodule