Business-code/fpga/rtl/reset_sync.v

`timescale 1ns/1ps

// Asynchronous assert, synchronous deassert reset conditioner.
// External KEY_1 is active-low.
module reset_sync(
    input  wire clk,
    input  wire reset_n_ext,
    output wire reset_n
);
    reg [1:0] sync_ff;

    always @(posedge clk or negedge reset_n_ext) begin
        if (!reset_n_ext)
            sync_ff <= 2'b00;
        else
            sync_ff <= {sync_ff[0], 1'b1};
    end

    assign reset_n = sync_ff[1];
endmodule