Business-code/fpga/rtl/motor_feedback_rx.v

`timescale 1ns/1ps

// Parse the same 16-byte A5 5A framed protocol used by trace_packet_tx.
// Only packet type 0x91 (PC -> FPGA MOTOR_FEEDBACK) is accepted.
module motor_feedback_rx (
    input  wire        clk,
    input  wire        reset_n,
    input  wire [7:0]  rx_data,
    input  wire        rx_valid,

    output reg         feedback_valid,
    output reg  [15:0] feedback_seq,
    output reg  [15:0] feedback_flags,
    output reg  [31:0] feedback_timestamp,
    output reg  [15:0] feedback_rpm,
    output reg  [15:0] feedback_current_ma,
    output reg         crc_error
);
    localparam [7:0] PKT_MOTOR_FB = 8'h91;
    localparam [1:0] R_SYNC_A5 = 2'd0;
    localparam [1:0] R_SYNC_5A = 2'd1;
    localparam [1:0] R_BODY    = 2'd2;

    reg [1:0] state;
    reg [4:0] index;
    reg [7:0] crc;
    reg [7:0] type_l;
    reg [15:0] seq_l;
    reg [15:0] flags_l;
    reg [31:0] time_l;
    reg [31:0] data_l;

    function [7:0] crc8_update;
        input [7:0] crc_in;
        input [7:0] data_in;
        integer i;
        reg [7:0] c;
        begin
            c = crc_in ^ data_in;
            for (i = 0; i < 8; i = i + 1) begin
                if (c[7])
                    c = (c << 1) ^ 8'h07;
                else
                    c = (c << 1);
            end
            crc8_update = c;
        end
    endfunction

    always @(posedge clk or negedge reset_n) begin
        if (!reset_n) begin
            state              <= R_SYNC_A5;
            index              <= 5'd0;
            crc                <= 8'd0;
            type_l             <= 8'd0;
            seq_l              <= 16'd0;
            flags_l            <= 16'd0;
            time_l             <= 32'd0;
            data_l             <= 32'd0;
            feedback_valid     <= 1'b0;
            feedback_seq       <= 16'd0;
            feedback_flags     <= 16'd0;
            feedback_timestamp <= 32'd0;
            feedback_rpm       <= 16'd0;
            feedback_current_ma<= 16'd0;
            crc_error          <= 1'b0;
        end else begin
            feedback_valid <= 1'b0;
            crc_error      <= 1'b0;

            if (rx_valid) begin
                case (state)
                    R_SYNC_A5: begin
                        if (rx_data == 8'hA5)
                            state <= R_SYNC_5A;
                    end

                    R_SYNC_5A: begin
                        if (rx_data == 8'h5A) begin
                            state <= R_BODY;
                            index <= 5'd2;
                            crc   <= 8'h00;
                        end else if (rx_data != 8'hA5) begin
                            state <= R_SYNC_A5;
                        end
                    end

                    R_BODY: begin
                        if (index <= 5'd14)
                            crc <= crc8_update(crc, rx_data);

                        case (index)
                            5'd2:  type_l       <= rx_data;
                            5'd3:  seq_l[15:8]  <= rx_data;
                            5'd4:  seq_l[7:0]   <= rx_data;
                            5'd5:  flags_l[15:8]<= rx_data;
                            5'd6:  flags_l[7:0] <= rx_data;
                            5'd7:  time_l[31:24]<= rx_data;
                            5'd8:  time_l[23:16]<= rx_data;
                            5'd9:  time_l[15:8] <= rx_data;
                            5'd10: time_l[7:0]  <= rx_data;
                            5'd11: data_l[31:24]<= rx_data;
                            5'd12: data_l[23:16]<= rx_data;
                            5'd13: data_l[15:8] <= rx_data;
                            5'd14: data_l[7:0]  <= rx_data;
                            default: begin end
                        endcase

                        if (index == 5'd15) begin
                            if (rx_data == crc) begin
                                if (type_l == PKT_MOTOR_FB) begin
                                    feedback_seq        <= seq_l;
                                    feedback_flags      <= flags_l;
                                    feedback_timestamp  <= time_l;
                                    feedback_rpm        <= data_l[31:16];
                                    feedback_current_ma <= data_l[15:0];
                                    feedback_valid      <= 1'b1;
                                end
                            end else begin
                                crc_error <= 1'b1;
                            end
                            state <= R_SYNC_A5;
                            index <= 5'd0;
                        end else begin
                            index <= index + 1'b1;
                        end
                    end

                    default: state <= R_SYNC_A5;
                endcase
            end
        end
    end
endmodule