`timescale 1ns/1ps module pwm_control_demo ( input wire clk, input wire reset_n, // Control command: -128 .. +127 input wire signed [7:0] cmd, // Safety/control signals input wire enable, input wire fault, // Observable internal results output reg signed [7:0] limited_cmd, output reg direction, output reg [6:0] duty, // Actual PWM waveform output wire pwm_out ); // 0..99 PWM carrier counter reg [6:0] pwm_counter; // --------------------------------------------------------- // 1. Saturation limiter: command limited to -90 .. +90 // 2. Sign -> direction // 3. Absolute value -> PWM duty // --------------------------------------------------------- always @(*) begin if (cmd > 8'sd90) limited_cmd = 8'sd90; else if (cmd < -8'sd90) limited_cmd = -8'sd90; else limited_cmd = cmd; if (limited_cmd < 0) begin direction = 1'b1; // reverse duty = -limited_cmd; end else begin direction = 1'b0; // forward duty = limited_cmd; end end // --------------------------------------------------------- // PWM carrier: 0,1,2 ... 99,0,1... // --------------------------------------------------------- always @(posedge clk or negedge reset_n) begin if (!reset_n) pwm_counter <= 7'd0; else if (pwm_counter == 7'd99) pwm_counter <= 7'd0; else pwm_counter <= pwm_counter + 1'b1; end // --------------------------------------------------------- // PWM output // // duty=25 -> 25 high clocks / 100 clocks = 25% // // enable=0 or fault=1 -> PWM forced OFF // --------------------------------------------------------- assign pwm_out = reset_n && enable && !fault && (pwm_counter < duty); endmodule //CI rollout test //automatic trigger test // poll scm trigger test // argo events test // full automatic ci test // webhook delivery test